GitHub - naman-ranka/mips-processor: 5-stage pipelined MIPS processor in SystemVerilog — 33 instructions, 12-path forwarding, CAM instruction cache, LL/SC atomics · GitHub

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mips-processor

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5-stage pipelined MIPS processor in SystemVerilog — 33 instructions, 12-path forwarding, CAM instruction cache, LL/SC atomics

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Name		Name	Last commit message	Last commit date
.vscode		.vscode
archive		archive
.gitignore		.gitignore
alu.sv		alu.sv
ca_ctrl.sv		ca_ctrl.sv
cam2.sv		cam2.sv
cam_params.vh		cam_params.vh
common.vh		common.vh
cpu5.sv		cpu5.sv
cpu_params.vh		cpu_params.vh
equality.sv		equality.sv
forward.sv		forward.sv
instr_reg.sv		instr_reg.sv
instr_reg_params.vh		instr_reg_params.vh
memory.sv		memory.sv
memory_defines.vh		memory_defines.vh
memory_params.vh		memory_params.vh
pc.sv		pc.sv
pipe_ex_mem.sv		pipe_ex_mem.sv
pipe_id_ex.sv		pipe_id_ex.sv
pipe_mem_wb.sv		pipe_mem_wb.sv
regfile.sv		regfile.sv
regfile_defines.vh		regfile_defines.vh
regfile_params.vh		regfile_params.vh
top_cpu5.sv		top_cpu5.sv

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5-stage pipelined MIPS processor in SystemVerilog — 33 instructions, 12-path forwarding, CAM instruction cache, LL/SC atomics

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