pipe_mem_wb.sv

// Pipeline register: MEM/WB (Stage 4 → Stage 5)
module pipe_mem_wb
  #(
    parameter BITS = 32,
    parameter REG_ADDR_BITS = 5
  )
  (
    input  logic                      clk,
    input  logic                      rst_,
    
    // Stage 4 inputs
    input  logic [BITS-1:0]           alu_out_s4,
    input  logic [BITS-1:0]           d_mem_rdata,
    input  logic [REG_ADDR_BITS-1:0]  waddr_s4,
    input  logic                      rw_s4,
    input  logic                      sel_mem_s4,
    input  logic [3:0]                byte_en_s4,
    input  logic                      halt_s4,
    input  logic                      atomic_s4,
    input  logic                      link_rw_,
    input  logic                      sc_success_s4,
    
    // Stage 5 outputs
    output logic [BITS-1:0]           alu_out_s5,
    output logic [BITS-1:0]           d_mem_rdata_s5,
    output logic [REG_ADDR_BITS-1:0]  waddr_s5,
    output logic                      rw_s5,
    output logic                      sel_mem_s5,
    output logic [3:0]                byte_en_s5,
    output logic                      halt_s5,
    output logic                      atomic_s5,
    output logic                      link_rw_s5,
    output logic                      sc_success_s5
  );

  always_ff @(posedge clk or negedge rst_) begin
    if (!rst_) begin
      alu_out_s5      <= {BITS{1'b0}};
      d_mem_rdata_s5  <= {BITS{1'b0}};
      waddr_s5        <= {REG_ADDR_BITS{1'b0}};
      rw_s5           <= 1'b1;  // No write
      sel_mem_s5      <= 1'b0;
      byte_en_s5      <= 4'hF;
      halt_s5         <= 1'b0;
      atomic_s5       <= 1'b0;
      link_rw_s5      <= 1'b1;  // No write
      sc_success_s5   <= 1'b0;  // SC failed
    end else begin
      alu_out_s5      <= alu_out_s4;
      d_mem_rdata_s5  <= d_mem_rdata;
      waddr_s5        <= waddr_s4;
      rw_s5           <= rw_s4;
      sel_mem_s5      <= sel_mem_s4;
      byte_en_s5      <= byte_en_s4;
      halt_s5         <= halt_s4;
      atomic_s5       <= atomic_s4;
      link_rw_s5      <= link_rw_;
      sc_success_s5   <= sc_success_s4;
    end
  end

endmodule