top_cpu5.sv

// test bench for the cpu
module top_cpu5();

   //logic [31:0] rdata;
   logic        halt;
   logic        exception;

   logic         clk;
   logic         rst_;
   logic  [31:0] counter;

   initial // read the array to load the program
   begin
     $readmemh("prog_cache_test_i.txt",cpu.i_memory.mem); // loading the memory
     $display("DEBUG: Loaded instruction memory:");
     for ( integer ind = 0 ; ind < 10 ; ind++ )
        $display("  memory[%d] = %h", ind, cpu.i_memory.mem[ind]);
   end

   cpu5 #(
      .CACHE_ENTRIES(8),
      .CACHE_TAGSZ(32)
   ) cpu( .halt(halt), .exception(exception), .clk(clk), .rst_(rst_) );

   // Register monitoring signals for waveform viewing
   logic [31:0] t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
   logic [31:0] s0, s1, s2, s3, s4, s5, s6, s7, s8;
   
   assign t0 = cpu.regfile.mem[8];
   assign t1 = cpu.regfile.mem[9];
   assign t2 = cpu.regfile.mem[10];
   assign t3 = cpu.regfile.mem[11];
   assign t4 = cpu.regfile.mem[12];
   assign t5 = cpu.regfile.mem[13];
   assign t6 = cpu.regfile.mem[14];
   assign t7 = cpu.regfile.mem[15];
   assign t8 = cpu.regfile.mem[24];
   assign t9 = cpu.regfile.mem[25];
   
   assign s0 = cpu.regfile.mem[16];
   assign s1 = cpu.regfile.mem[17];
   assign s2 = cpu.regfile.mem[18];
   assign s3 = cpu.regfile.mem[19];
   assign s4 = cpu.regfile.mem[20];
   assign s5 = cpu.regfile.mem[21];
   assign s6 = cpu.regfile.mem[22];
   assign s7 = cpu.regfile.mem[23];
   assign s8 = cpu.regfile.mem[30];

   initial
   begin
     clk <= 1'b0;
     rst_ <= 1'b0;
     counter <= 32'h0;
     #10 rst_ <= 1'b1;
     while ( 1 )
     begin
        #10 clk <= 1'b1;
        #10 clk <= 1'b0;
     end
   end

   always @ ( * )
   begin
      if ( ( rst_ == 1'b1 ) && ( exception == 1'b1 ) && ( halt == 1'b0 ) )
        $display("Illegal Instruction @ cycle %d", counter);
   end

   always @ ( posedge clk )
   begin
      if ( halt == 1'b1 ) begin
         $display("HALT detected at cycle %d", counter);
         $finish;
      end
      // Debug: print JAL execution
      if (cpu.regfile.jal) begin
         $display("Cycle %d: JAL executing, pc_addr = 0x%h, writing $ra = 0x%h", counter, cpu.regfile.pc_addr, cpu.regfile.pc_addr + 1);
      end
      // Debug: print JR execution and PC updates
      if (cpu.jreg) begin
         $display("Cycle %d: JR executing, r1_data = 0x%h, jr_target = 0x%h, j_fwd_s4 = %b, j_fwd_s5 = %b, next_pc = 0x%h, pc_addr = 0x%h", 
                  counter, cpu.pc.r1_data, cpu.pc.jr_target, cpu.j_fwd_s4, cpu.j_fwd_s5, cpu.pc.next_pc, cpu.pc_addr);
      end
      // Debug: print branch execution
      if (cpu.breq || cpu.brne) begin
         $display("Cycle %d: BRANCH executing, breq=%b, brne=%b, equal=%b, stall=%b, b_r1_fwd_s4=%b, b_r1_fwd_s5=%b, b_r2_fwd_s4=%b, b_r2_fwd_s5=%b", 
                  counter, cpu.breq, cpu.brne, cpu.equal, cpu.stall_pipe, cpu.b_r1_fwd_s4, cpu.b_r1_fwd_s5, cpu.b_r2_fwd_s4, cpu.b_r2_fwd_s5);
      end
      $display("Cycle %d: pc_addr = 0x%h, instr_word = 0x%h, halt = %b", counter, cpu.pc_addr, cpu.instr_word, cpu.halt);
      // Debug: print memory writes
      if (cpu.d_memory.rw_ == 1'b0) begin
         $display("Cycle %d: Memory WRITE addr=0x%h, data=0x%h", counter, cpu.d_memory.addr, cpu.d_memory.wdata);
      end
      // Debug: print register writes
      if (cpu.regfile.rw_ == 1'b0 && cpu.regfile.waddr != 0) begin
         $display("Cycle %d: Writing r%d = 0x%h", counter, cpu.regfile.waddr, cpu.regfile.wdata);
      end
   end

   always @ ( negedge clk )
   begin
     if ( rst_ == 1'b1 )
       counter <= counter + 1;
     if ( halt || exception )
     begin
       #5;
       $finish;
     end
   end

  final   // dump the regfile to verify things worked
  begin
     $display("\n========================================");
     $display("SIMULATION COMPLETE - Final Register Values");
     $display("========================================");
     $display("Cycles executed: %d", counter);
     $display("\nRegister File Contents:");
     $display("----------------------------------------");
     $display("  r 0 = 0x%08h", cpu.regfile.mem[0]);
     $display("  r 2 ($v0) = 0x%08h", cpu.regfile.mem[2]);
     $display("  r 3 ($v1) = 0x%08h", cpu.regfile.mem[3]);
     $display("  r 4 ($a0) = 0x%08h", cpu.regfile.mem[4]);
     $display("  r 5 ($a1) = 0x%08h", cpu.regfile.mem[5]);
     $display("  r 6 ($a2) = 0x%08h", cpu.regfile.mem[6]);
     $display("  r 7 ($a3) = 0x%08h", cpu.regfile.mem[7]);
     $display("  r 8 ($t0) = 0x%08h", cpu.regfile.mem[8]);
     $display("  r 9 ($t1) = 0x%08h", cpu.regfile.mem[9]);
     $display("  r10 ($t2) = 0x%08h", cpu.regfile.mem[10]);
     $display("  r11 ($t3) = 0x%08h", cpu.regfile.mem[11]);
     $display("  r12 ($t4) = 0x%08h", cpu.regfile.mem[12]);
     $display("  r13 ($t5) = 0x%08h", cpu.regfile.mem[13]);
     $display("  r14 ($t6) = 0x%08h", cpu.regfile.mem[14]);
     $display("  r15 ($t7) = 0x%08h", cpu.regfile.mem[15]);
     $display("  r16 ($s0) = 0x%08h", cpu.regfile.mem[16]);
     $display("  r17 ($s1) = 0x%08h", cpu.regfile.mem[17]);
     $display("  r18 ($s2) = 0x%08h", cpu.regfile.mem[18]);
     $display("  r19 ($s3) = 0x%08h", cpu.regfile.mem[19]);
     $display("  r20 ($s4) = 0x%08h", cpu.regfile.mem[20]);
     $display("  r21 ($s5) = 0x%08h", cpu.regfile.mem[21]);
     $display("  r22 ($s6) = 0x%08h", cpu.regfile.mem[22]);
     $display("  r23 ($s7) = 0x%08h", cpu.regfile.mem[23]);
     $display("  r24 ($t8) = 0x%08h", cpu.regfile.mem[24]);
     $display("========================================\n");
  end

  initial
  begin
    $dumpfile("wave.vcd");      // dump the waves to view on your laptop
    $dumpvars(0,top_cpu5);
  end
endmodule