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9 Open 6 Closed
9 Open 6 Closed
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Issues list

Reliable Node Extractor for VHDL/Verilog enhancement New feature or request help wanted Extra attention is needed
#24 opened Nov 9, 2024 by HendrikMennen
Associate Log Messages with Projects enhancement New feature or request
#22 opened Oct 30, 2024 by HendrikMennen
No Nodes Created for Generic Vector Length in Entity
#18 opened Oct 15, 2024 by swittlich
3
Define CompileExclude / Testbench as pattern in .fpgaproj file enhancement New feature or request
#16 opened Oct 2, 2024 by HendrikMennen
@HendrikMennen
GIT Support Tasks
#12 opened Aug 9, 2024 by HendrikMennen
2 of 3 tasks
@HendrikMennen
1
SVG generation with one click enhancement New feature or request
#9 opened Jul 25, 2024 by std-rubic
1
Add GHW, FST Parser enhancement New feature or request help wanted Extra attention is needed
#4 opened Jul 16, 2024 by HendrikMennen
Document Outline View enhancement New feature or request
#3 opened Mar 27, 2024 by std-rubic
Design Hierarchy View enhancement New feature or request
#2 opened Mar 27, 2024 by std-rubic
ProTip! What’s not been updated in a month: updated:<2024-10-14.