8364305: Support AVX10 saturating floating point conversion instructions #26919

missa-prime · 2025-08-25T05:20:23Z

Intel® AVX10 ISA [1] extensions added new saturating floating point conversion instructions which comply with definitions in section 5.8 of the 2019 IEEE-754 standard. They can compute floating point to integral type conversions while also handling special inputs such as NaN, +Infinity, and -Infinity.

Without AVX10.2, the current approach starts by converting the floating point value(s) in the source register to the desired integral value(s) in the destination register. In the scalar case, the CVTTSS2SI (single precision) or CVTTSD2SI (double precision) instruction is used. In the vector case, the CVTTPS2DQ (single precision) or CVTTPD2DQ (double precision) is used. However, if the source contains a special value (NaN, -Infinity, +Infinity, <= Integer.MIN_VALUE, or >= Integer.MAX_VALUE), extra handling is required. The specific sequence of instructions involved depends on the source (single precision vs double precision), destination (long, integer, short, or byte), level of parallelization (scalar vs vector), and supported AVX extension type. Essentially though, the special values are mapped to values (NaN -> 0, -Infinity, <= Integer.MIN_VALUE -> Integer.MIN_VALUE, +Infinity, >= Integer.MAX_VALUE -> Integer.MAX_VALUE) in the integer range with the help of a few temporary registers to store intermediate results.

This change uses the new AVX10.2 scalar (VCVTTSS2SIS or VCVTTSD2SIS) and vector (VCVTTPS2QQS, VCVTTPS2DQS, VCVTTPD2QQS, and VCVTTPD2DQS) instructions on supported platforms to avoid the extra handling described above. Also, the JTREG tests listed below were used to verify correctness with -XX:-UseSuperWord / -XX:+UseSuperWord options to exercise both scalar and vector paths. The baseline build used is OpenJDK v26-b11.

jtreg:test/hotspot/jtreg/compiler/codegen/TestByteDoubleVect.java
jtreg:test/hotspot/jtreg/compiler/codegen/TestByteFloatVect.java
jtreg:test/hotspot/jtreg/compiler/codegen/TestIntDoubleVect.java
jtreg:test/hotspot/jtreg/compiler/codegen/TestIntFloatVect.java
jtreg:test/hotspot/jtreg/compiler/codegen/TestLongDoubleVect.java
jtreg:test/hotspot/jtreg/compiler/codegen/TestLongFloatVect.java
jtreg:test/hotspot/jtreg/compiler/codegen/TestShortDoubleVect.java
jtreg:test/hotspot/jtreg/compiler/codegen/TestShortFloatVect.java
jtreg:test/hotspot/jtreg/compiler/vectorapi/VectorFPtoIntCastTest.java
jtreg:test/hotspot/jtreg/compiler/vectorization/runner/ArrayTypeConvertTest.java

[1] https://www.intel.com/content/www/us/en/content-details/856721/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html?wapkw=AVX10

Progress

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Issue

JDK-8364305: Support AVX10 saturating floating point conversion instructions (Enhancement - P4)

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Using Webrev

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…uctions

bridgekeeper · 2025-08-25T05:20:58Z

👋 Welcome back missa! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

openjdk · 2025-08-25T05:21:25Z

❗ This change is not yet ready to be integrated.
See the Progress checklist in the description for automated requirements.

openjdk · 2025-08-25T05:21:53Z

@missa-prime The following label will be automatically applied to this pull request:

hotspot-compiler

When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing list. If you would like to change these labels, use the /label pull request command.

mlbridge · 2025-08-25T23:43:01Z

Webrevs

jatin-bhateja · 2025-08-26T18:49:51Z

src/hotspot/cpu/x86/x86.ad

@@ -7753,6 +7773,20 @@ instruct castDtoX_reg_evex(vec dst, vec src, vec xtmp1, vec xtmp2, kReg ktmp1, k
  ins_pipe( pipe_slow );
 %}

+instruct cast2DtoX_reg_evex(vec dst, vec src, rFlagsReg cr) %{


Vector instruction do not effect EFLAGS register.

I removed the EFLAGS register parameters.

jatin-bhateja · 2025-08-26T18:50:03Z

src/hotspot/cpu/x86/x86.ad

+  predicate(VM_Version::supports_avx10_2() &&
+            is_integral_type(Matcher::vector_element_basic_type(n)));
+  match(Set dst (VectorCastD2X src));
+  effect(KILL cr);


Remove effect.

I removed the effect calls.

jatin-bhateja · 2025-08-26T18:51:36Z

src/hotspot/cpu/x86/x86.ad

@@ -7753,6 +7773,20 @@ instruct castDtoX_reg_evex(vec dst, vec src, vec xtmp1, vec xtmp2, kReg ktmp1, k
  ins_pipe( pipe_slow );
 %}

+instruct cast2DtoX_reg_evex(vec dst, vec src, rFlagsReg cr) %{


How about adding a CICS flavour of these patterns. As now we have a single instruction to cover entire conversion semantics memory operand patterns will be useful.

I'm not familiar with CICS. Could you elaborate? Also, I added memory variants.

jatin-bhateja · 2025-08-26T18:52:22Z

src/hotspot/cpu/x86/assembler_x86.cpp

@@ -2363,6 +2403,14 @@ void Assembler::evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
  emit_int16(0x7A, (0xC0 | encode));
 }

+void Assembler::evcvttpd2qqs(XMMRegister dst, XMMRegister src, int vector_len) {


Please also add memory operand flavour of these assembler routines.

I added memory variants of the instructions.

…tions

eme64 · 2025-08-28T13:33:27Z

@missa-prime Looks like an interesting patch! Do you think you could add some sort of IR test here, to verify that the correct code is generated on AVX10 vs lower AVX?

missa-prime · 2025-08-29T23:35:37Z

@missa-prime Looks like an interesting patch! Do you think you could add some sort of IR test here, to verify that the correct code is generated on AVX10 vs lower AVX?

@eme64 Thanks for the suggestion. This patch doesn't modify any IR though, so I'm not sure what IR test(s) to add. I could modify existing tests (test/hotspot/jtreg/compiler/vectorapi/VectorFPtoIntCastTest.java, test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java, test/hotspot/jtreg/compiler/vectorization/runner/ArrayTypeConvertTest.java) that use IR nodes as dependencies though. Would that be sufficient? Or did you have something else in mind?

…take memory as the source

eme64 · 2025-08-30T11:38:18Z

@missa-prime Could you not match on the mach graph? See example:
test/hotspot/jtreg/compiler/vectorapi/VectorMultiplyOpt.java with CompilePhase.FINAL_CODE.

Maybe another CompilePhase is better. I have never matched on the mach graph myself, but I wonder if it may be useful here.

jatin-bhateja · 2025-09-01T07:50:57Z

src/hotspot/cpu/x86/x86.ad

+instruct cast2DtoX_mem_evex(vec dst, memory src) %{
+  predicate(VM_Version::supports_avx10_2() &&
+            is_integral_type(Matcher::vector_element_basic_type(n)));
+  match(Set dst (VectorCastD2X src));


I assume your intent here is to feed the memory operand to the vector cast IR, a memory operand is first loaded into register using LoadVector IR, so a CISC / memory variant of pattern should consume the Load IR such that the operand is directly exposed to the instruction. Checkout https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/x86/x86.ad#L8986

Make a similar change in all the newly added memory patterns.

I updated the scalar and vector memory patterns. I'm not completely sure about the vector ones though, so I'll try and test further.

…tions that involve memory

…ure ID

jatin-bhateja · 2025-09-04T05:40:17Z

test/hotspot/jtreg/compiler/vectorapi/VectorFPtoIntCastTest.java

@@ -87,7 +87,7 @@ public VectorFPtoIntCastTest() {

    @Test
    @IR(counts = {IRNode.VECTOR_CAST_F2I, IRNode.VECTOR_SIZE_16, "> 0"},
-        applyIfCPUFeature = {"avx512f", "true"})
+        applyIfCPUFeatureOr = {"avx512f", "true", "avx10_2", "true"})


You should check for target specific Machine IR which is selected on AVX10_2 targets.

New checks are added.

jatin-bhateja · 2025-09-04T05:41:58Z

test/hotspot/jtreg/compiler/vectorapi/VectorFPtoIntCastTest.java

@@ -105,7 +105,7 @@ public void checkf2int(int len) {

    @Test
    @IR(counts = {IRNode.VECTOR_CAST_F2L, IRNode.VECTOR_SIZE_8, "> 0"},
-        applyIfCPUFeature = {"avx512dq", "true"})
+        applyIfCPUFeatureOr = {"avx512dq", "true", "avx10_2", "true"})


avx10_2 is super set of AVX512DQ, we enable all AVX512 featurs during VM initialization and IRFrameWork rely on the same.

I updated the checks to account for this.

missa-prime · 2025-09-06T00:28:18Z

@missa-prime Could you not match on the mach graph? See example: test/hotspot/jtreg/compiler/vectorapi/VectorMultiplyOpt.java with CompilePhase.FINAL_CODE.

Maybe another CompilePhase is better. I have never matched on the mach graph myself, but I wonder if it may be useful here.

I modified existing vector conversion tests, and I'll add some matching scalar tests to get full coverage.

…rms during Vector floating point to integer conversion tests

…bling vector alignment or compact object headers

jatin-bhateja · 2025-09-09T02:28:45Z

test/hotspot/jtreg/compiler/vectorization/runner/ArrayTypeConvertTest.java

+    @IR(counts = {"castDtoX", " >0 "}, phase = CompilePhase.FINAL_CODE,
+        applyIfCPUFeatureAnd = {"avx", "true", "avx10_2", "false"})
+    @IR(counts = {"cast2DtoX", " >0 "}, phase = CompilePhase.FINAL_CODE,
+        applyIfCPUFeature = {"avx10_2", "true"})


Please refer to https://github.com/openjdk/jdk/blob/master/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java#L2638 for adding MachNode IR node based checks

Thanks, I added some new nodes.

jatin-bhateja · 2025-09-10T18:12:34Z

@missa-prime , please have a look at the following failure with the current patch

2025-09-10T02:04:00.8424130Z 
2025-09-10T02:04:00.8424221Z Failed IR Rules (4) of Methods (4)
2025-09-10T02:04:00.8424462Z ----------------------------------
2025-09-10T02:04:00.8425011Z 1) Method "public char[] compiler.vectorization.runner.ArrayTypeConvertTest.convertDoubleToChar()" - [Failed IR rules: 1]:
2025-09-10T02:04:00.8426351Z    * @IR rule 3: "@compiler.lib.ir_framework.IR(phase={DEFAULT}, applyIfPlatformAnd={}, applyIfCPUFeatureOr={}, counts={"_#CAST_D2X#_", "> 0"}, failOn={}, applyIfPlatform={}, applyIfPlatformOr={}, applyIfOr={}, applyIfCPUFeatureAnd={"avx", "true", "avx10_2", "false"}, applyIf={}, applyIfCPUFeature={}, applyIfAnd={}, applyIfNot={})"
2025-09-10T02:04:00.8427967Z      > Phase "Final Code":
2025-09-10T02:04:00.8428412Z        - counts: Graph contains wrong number of nodes:
2025-09-10T02:04:00.8429037Z          * Constraint 1: "(\d+(\s){2}(castD2X_reg_(av|eve)x.*)+(\s){2}===.*)"
2025-09-10T02:04:00.8429650Z            - Failed comparison: [found] 0 > 0 [given]
2025-09-10T02:04:00.8430146Z            - No nodes matched!
2025-09-10T02:04:00.8430409Z 
2025-09-10T02:04:00.8431165Z 2) Method "public int[] compiler.vectorization.runner.ArrayTypeConvertTest.convertDoubleToInt()" - [Failed IR rules: 1]:
2025-09-10T02:04:00.8433283Z    * @IR rule 2: "@compiler.lib.ir_framework.IR(phase={DEFAULT}, applyIfPlatformAnd={}, applyIfCPUFeatureOr={}, counts={"_#CAST_D2X#_", "> 0"}, failOn={}, applyIfPlatform={}, applyIfPlatformOr={}, applyIfOr={}, applyIfCPUFeatureAnd={"avx", "true", "avx10_2", "false"}, applyIf={}, applyIfCPUFeature={}, applyIfAnd={}, applyIfNot={})"
2025-09-10T02:04:00.8434546Z      > Phase "Final Code":
2025-09-10T02:04:00.8434810Z        - counts: Graph contains wrong number of nodes:
2025-09-10T02:04:00.8435174Z          * Constraint 1: "(\d+(\s){2}(castD2X_reg_(av|eve)x.*)+(\s){2}===.*)"
2025-09-10T02:04:00.8435523Z            - Failed comparison: [found] 0 > 0 [given]
2025-09-10T02:04:00.8435792Z            - No nodes matched!
2025-09-10T02:04:00.8435937Z 
2025-09-10T02:04:00.8436340Z 3) Method "public short[] compiler.vectorization.runner.ArrayTypeConvertTest.convertDoubleToShort()" - [Failed IR rules: 1]:
2025-09-10T02:04:00.8437688Z    * @IR rule 3: "@compiler.lib.ir_framework.IR(phase={DEFAULT}, applyIfPlatformAnd={}, applyIfCPUFeatureOr={}, counts={"_#CAST_D2X#_", "> 0"}, failOn={}, applyIfPlatform={}, applyIfPlatformOr={}, applyIfOr={}, applyIfCPUFeatureAnd={"avx", "true", "avx10_2", "false"}, applyIf={}, applyIfCPUFeature={}, applyIfAnd={}, applyIfNot={})"
2025-09-10T02:04:00.8438703Z      > Phase "Final Code":
2025-09-10T02:04:00.8438956Z        - counts: Graph contains wrong number of nodes:
2025-09-10T02:04:00.8439301Z          * Constraint 1: "(\d+(\s){2}(castD2X_reg_(av|eve)x.*)+(\s){2}===.*)"
2025-09-10T02:04:00.8439647Z            - Failed comparison: [found] 0 > 0 [given]
2025-09-10T02:04:00.8439913Z            - No nodes matched!
2025-09-10T02:04:00.8440063Z 
2025-09-10T02:04:00.8440436Z 4) Method "public int[] compiler.vectorization.runner.ArrayTypeConvertTest.convertFloatToInt()" - [Failed IR rules: 1]:
2025-09-10T02:04:00.8441891Z    * @IR rule 2: "@compiler.lib.ir_framework.IR(phase={DEFAULT}, applyIfPlatformAnd={}, applyIfCPUFeatureOr={}, counts={"_#CAST_F2X#_", "> 0"}, failOn={}, applyIfPlatform={}, applyIfPlatformOr={}, applyIfOr={}, applyIfCPUFeatureAnd={"avx", "true", "avx10_2", "false"}, applyIf={}, applyIfCPUFeature={}, applyIfAnd={}, applyIfNot={})"
2025-09-10T02:04:00.8442912Z      > Phase "Final Code":
2025-09-10T02:04:00.8443155Z        - counts: Graph contains wrong number of nodes:
2025-09-10T02:04:00.8443492Z          * Constraint 1: "(\d+(\s){2}(castF2X_reg_(av|eve)x.*)+(\s){2}===.*)"
2025-09-10T02:04:00.8443951Z            - Failed comparison: [found] 0 > 0 [given]
2025-09-10T02:04:00.8444210Z            - No nodes matched!
2025-09-10T02:04:00.8444355Z 
2025-09-10T02:04:00.8444498Z >>> Check stdout for compilation output of the failed methods

…t in cast2F2X and cast2D2X memory instructions

… conversion tests

sviswa7 · 2025-09-11T16:54:32Z

test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

@@ -491,6 +491,26 @@ public class IRNode {
        callOfNodes(STATIC_CALL_OF_METHOD, "CallStaticJava");
    }

+    public static final String CAST_F2X = PREFIX + "CAST_F2X" + POSTFIX;
+    static {
+        machOnlyNameRegex(CAST_F2X, "castF2X_reg_(av|eve)x");


This should be "castFtoX_reg_(av|eve)x".

sviswa7 · 2025-09-11T16:55:50Z

test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

+
+    public static final String CAST_D2X = PREFIX + "CAST_D2X" + POSTFIX;
+    static {
+        machOnlyNameRegex(CAST_D2X, "castD2X_reg_(av|eve)x");


This should be "castDtoX_reg_(av|eve)x".

sviswa7 · 2025-09-11T16:56:13Z

test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

+
+    public static final String CAST2_F2X = PREFIX + "CAST2_F2X" + POSTFIX;
+    static {
+        machOnlyNameRegex(CAST2_F2X, "cast2F2X_(reg|mem)_evex");


This should be "cast2FtoX_(reg|mem)_evex"

sviswa7 · 2025-09-11T16:56:54Z

test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

+
+    public static final String CAST2_D2X = PREFIX + "CAST2_D2X" + POSTFIX;
+    static {
+        machOnlyNameRegex(CAST2_D2X, "cast2D2X_(reg|mem)_evex");


This should be "cast2DtoX_(reg|mem)_evex".

jatin-bhateja · 2025-09-11T17:20:29Z

src/hotspot/cpu/x86/x86.ad

+  predicate(VM_Version::supports_avx10_2() &&
+            is_integral_type(Matcher::vector_element_basic_type(n)));
+  match(Set dst (VectorCastF2X src));
+  format %{ "vector_cast2r_f2x $dst, $src\t!" %}


Suggested change

format %{ "vector_cast2r_f2x $dst, $src\t!" %}

format %{ "vector_cast_f2x_saturating $dst, $src\t!" %}

jatin-bhateja · 2025-09-11T17:24:25Z

src/hotspot/cpu/x86/x86.ad

+  predicate(VM_Version::supports_avx10_2() &&
+            is_integral_type(Matcher::vector_element_basic_type(n)));
+  match(Set dst (VectorCastF2X (LoadVector src)));
+  format %{ "vector_cast2m_f2x $dst, $src\t!" %}


Suggested change

format %{ "vector_cast2m_f2x $dst, $src\t!" %}

format %{ "vector_cast_f2x_saturating $dst, $src\t!" %}

src will be represented by appropriate addressing scheme for the memory operand

jatin-bhateja · 2025-09-11T17:25:05Z

src/hotspot/cpu/x86/x86.ad

+  predicate(VM_Version::supports_avx10_2() &&
+            is_integral_type(Matcher::vector_element_basic_type(n)));
+  match(Set dst (VectorCastD2X src));
+  format %{ "vector_cast2r_d2x $dst, $src\t!" %}


Suggested change

format %{ "vector_cast2r_d2x $dst, $src\t!" %}

format %{ "vector_cast_d2x_saturating $dst, $src\t!" %}

jatin-bhateja · 2025-09-11T17:25:23Z

src/hotspot/cpu/x86/x86.ad

+  predicate(VM_Version::supports_avx10_2() &&
+            is_integral_type(Matcher::vector_element_basic_type(n)));
+  match(Set dst (VectorCastD2X (LoadVector src)));
+  format %{ "vector_cast2m_d2x $dst, $src\t!" %}


Suggested change

format %{ "vector_cast2m_d2x $dst, $src\t!" %}

format %{ "vector_cast_d2x_saturating $dst, $src\t!" %}

sviswa7 · 2025-09-11T20:42:16Z

src/hotspot/cpu/x86/x86.ad

@@ -7709,6 +7712,33 @@ instruct castFtoX_reg_evex(vec dst, vec src, vec xtmp1, vec xtmp2, kReg ktmp1, k
  ins_pipe( pipe_slow );
 %}

+instruct cast2FtoX_reg_evex(vec dst, vec src) %{


Could be named as castFtoX_reg_avx10.

sviswa7 · 2025-09-11T20:42:43Z

src/hotspot/cpu/x86/x86.ad

+  ins_pipe( pipe_slow );
+%}
+
+instruct cast2FtoX_mem_evex(vec dst, memory src) %{


Could be named as castFtoX_mem_avx10.

sviswa7 · 2025-09-11T20:43:50Z

src/hotspot/cpu/x86/x86.ad

@@ -7753,6 +7786,33 @@ instruct castDtoX_reg_evex(vec dst, vec src, vec xtmp1, vec xtmp2, kReg ktmp1, k
  ins_pipe( pipe_slow );
 %}

+instruct cast2DtoX_reg_evex(vec dst, vec src) %{


Could be named as castDtoX_reg_avx10.

sviswa7 · 2025-09-11T20:45:14Z

src/hotspot/cpu/x86/x86.ad

+  ins_pipe( pipe_slow );
+%}
+
+instruct cast2DtoX_mem_evex(vec dst, memory src) %{


Could be named as castDtoX_mem_avx10.

sviswa7 · 2025-09-11T20:45:49Z

src/hotspot/cpu/x86/x86_64.ad

@@ -11724,8 +11725,31 @@ instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
  ins_pipe(pipe_slow);
 %}

+instruct conv2F2I_reg_reg(rRegI dst, regF src)


Could be named as convF2I_reg_reg_avx10.

sviswa7 · 2025-09-11T20:48:55Z

src/hotspot/cpu/x86/x86_64.ad

@@ -11746,8 +11793,31 @@ instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
  ins_pipe(pipe_slow);
 %}

+instruct conv2D2I_reg_reg(rRegI dst, regD src)


Could be named as convD2I_reg_reg_avx10.

sviswa7 · 2025-09-11T20:49:23Z

src/hotspot/cpu/x86/x86_64.ad

+  ins_pipe(pipe_slow);
+%}
+
+instruct conv2D2I_reg_mem(rRegI dst, memory src)


Could be named as convD2I_reg_mem_avx10.

sviswa7 · 2025-09-11T20:49:51Z

src/hotspot/cpu/x86/x86_64.ad

@@ -11757,6 +11827,28 @@ instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
  ins_pipe(pipe_slow);
 %}

+instruct conv2D2L_reg_reg(rRegL dst, regD src)


Could be named as convD2L_reg_reg_avx10.

sviswa7 · 2025-09-11T20:50:12Z

src/hotspot/cpu/x86/x86_64.ad

+  ins_pipe(pipe_slow);
+%}
+
+instruct conv2D2L_reg_mem(rRegL dst, memory src)


Could be named as convD2L_reg_mem_avx10.

IRNode.java will need name regex changes accordingly.

sviswa7 · 2025-09-11T20:58:15Z

test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

@@ -491,6 +491,26 @@ public class IRNode {
        callOfNodes(STATIC_CALL_OF_METHOD, "CallStaticJava");
    }

+    public static final String CAST_F2X = PREFIX + "CAST_F2X" + POSTFIX;


May be we can name CAST_F2X as X86_VCAST_F2X and CAST2_F2X as X86_VCAST_F2X_AVX10.
Then we can use the similar theme for other names below as well.

Enable new AVX 10.2 vector and scalar floating point conversion instr…

57745ae

…uctions

openjdk bot added the hotspot-compiler [email protected] label Aug 25, 2025

missa-prime marked this pull request as ready for review August 25, 2025 23:37

openjdk bot added the rfr Pull request is ready for review label Aug 25, 2025

jatin-bhateja reviewed Aug 26, 2025

View reviewed changes

Add memory variants of the AVX 10.2 floating point conversion instruc…

e67e376

…tions

Fix input size enum values for AVX 10.2 conversion instructions that …

be5c0b4

…take memory as the source

jatin-bhateja reviewed Sep 1, 2025

View reviewed changes

missa-prime added 3 commits September 3, 2025 17:19

Correct matching rules for AVX 10.2 floating point conversion instruc…

9d7484c

…tions that involve memory

Update floating point conversion tests to check for AVX 10.2 CPU feat…

07ac817

…ure ID

Add AVX 10.2 CPU feature flag to list of verified ones

e0c84f6

jatin-bhateja reviewed Sep 4, 2025

View reviewed changes

Fix match rule for AVX 10.2 double to long scalar conversion

a38060e

missa-prime added 4 commits September 5, 2025 17:28

Add new IR rules to vector float to integer conversion tests

6407cc4

Avoid machine instruction searches in IR rules for non-AVX10.2 platfo…

709b443

…rms during Vector floating point to integer conversion tests

Use applyIfCPUFeatureAnd to check multiple CPU feature pairs in tests

b7d3ae3

Check for scalar casting instead of vector casting in tests when disa…

4d8f3ab

…bling vector alignment or compact object headers

jatin-bhateja reviewed Sep 9, 2025

View reviewed changes

Add new IR nodes covering x86 floating point conversion instructions

bc59e4d

missa-prime added 2 commits September 10, 2025 16:34

Correctly calculate vector lengths and don't rely on VectorReinterpre…

7202ec4

…t in cast2F2X and cast2D2X memory instructions

Check for instructions that shouldn't appear in vector floating point…

8587952

… conversion tests

sviswa7 reviewed Sep 11, 2025

View reviewed changes

jatin-bhateja reviewed Sep 11, 2025

View reviewed changes

sviswa7 reviewed Sep 11, 2025

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	format %{ "vector_cast2r_f2x $dst, $src\t!" %}
	format %{ "vector_cast_f2x_saturating $dst, $src\t!" %}

	format %{ "vector_cast2m_f2x $dst, $src\t!" %}
	format %{ "vector_cast_f2x_saturating $dst, $src\t!" %}

	format %{ "vector_cast2r_d2x $dst, $src\t!" %}
	format %{ "vector_cast_d2x_saturating $dst, $src\t!" %}

	format %{ "vector_cast2m_d2x $dst, $src\t!" %}
	format %{ "vector_cast_d2x_saturating $dst, $src\t!" %}

8364305: Support AVX10 saturating floating point conversion instructions #26919

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8364305: Support AVX10 saturating floating point conversion instructions #26919

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missa-prime commented Aug 25, 2025 •

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