8359378: aarch64: crash when using -XX:+UseFPUForSpilling #27350
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AArch64 BarrierSetAssembler path assumes only FP/vector ideal regs reach the FP spill/restore encoding. With -XX:+UseFPUForSpilling Register Allocator may allocate scalar values in FP registers. When such values (Op_RegI/Op_RegN/Op_RegL/Op_RegP) hit
BarrierSetAssembler::encode_float_vector_register_size
, we trip ShouldNotReachHere in release build and "unexpected ideal register" assertion in debug build.Fix: teach the encoder to handle scalar ideal regs when they physically live in FP regs:
Related:
Testing: tier1-3 with javaoptions -Xcomp -Xbatch -XX:+UseFPUForSpilling on AARCH
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