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@bulasevich bulasevich commented Sep 17, 2025

AArch64 BarrierSetAssembler path assumes only FP/vector ideal regs reach the FP spill/restore encoding. With -XX:+UseFPUForSpilling Register Allocator may allocate scalar values in FP registers. When such values (Op_RegI/Op_RegN/Op_RegL/Op_RegP) hit BarrierSetAssembler::encode_float_vector_register_size, we trip ShouldNotReachHere in release build and "unexpected ideal register" assertion in debug build.

Fix: teach the encoder to handle scalar ideal regs when they physically live in FP regs:

  • treat Op_RegI / Op_RegN as 32-bit (single slot) - same class as Op_RegF
  • treat Op_RegL / Op_RegP as 64-bit (two slots) - same class as Op_RegD

Related:

Testing: tier1-3 with javaoptions -Xcomp -Xbatch -XX:+UseFPUForSpilling on AARCH


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  • JDK-8359378: aarch64: crash when using -XX:+UseFPUForSpilling (Bug - P3)

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bridgekeeper bot commented Sep 17, 2025

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openjdk bot commented Sep 17, 2025

@bulasevich The following label will be automatically applied to this pull request:

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@bulasevich bulasevich changed the title 8359378: arch64: crash when using -XX:+UseFPUForSpilling arch64: crash when using -XX:+UseFPUForSpilling Sep 17, 2025
@bulasevich bulasevich changed the title arch64: crash when using -XX:+UseFPUForSpilling 8359378: aarch64: crash when using -XX:+UseFPUForSpilling Sep 17, 2025
@bulasevich bulasevich marked this pull request as ready for review September 17, 2025 17:29
@openjdk openjdk bot added the rfr Pull request is ready for review label Sep 17, 2025
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