Caravel Leros Project

This is a user project for the Caravel harness, integrating the open-source Leros CPU core. This repository contains the DTU subsystem from the Edu4Chip tapeout project.

Checkout with submodules:

git clone --recurse-submodules git@github.com:os-chip-design/caravel_leros_2025.git

Or later:

git submodule update --init --recursive

Then start Docker and follow the Docs, or as follows:

make setup

Install the CF RAM and the DFF RAM (it should be included in the Makefile on Linux, below is for Mac), using the available Python virtual environment venv:

source venv/bin/activate
pip install cf-ipm
ipm install CF_SRAM_1024x32
ipm install DFFRAM256x32
deactivate

Generate the Leros Verilog files (not needed on a clean checkout as the SV files are included):

make generate-verilog

You can harden all blocks one by one starting with the wrapper for the ChipFoundry SRAM:

make CF_SRAM_1024x32_wrapper LIBRELANE_USE_NIX=1

and the register file

make reg-file LIBRELANE_USE_NIX=1

and the register based memories

make regmem_128 LIBRELANE_USE_NIX=1
make regmem_256 LIBRELANE_USE_NIX=1

then build and harden different Leros versions:

make leros-cfram LIBRELANE_USE_NIX=1
make leros-openram LIBRELANE_USE_NIX=1
make leros-dffram LIBRELANE_USE_NIX=1
make leros-regmem LIBRELANE_USE_NIX=1

and then include all in the wrapper for Caravel:

make user_project_wrapper LIBRELANE_USE_NIX=1

You can also harden all blocks and the top level in one go with

make -j 4 harden-all LIBRELANE_USE_NIX=1 PARALLEL=1

where the PARALLEL variable enables parallel building of the blocks.

Note that the LIBRELANE_USE_NIX=1 can speedup the builds with Nix is installed. However, it does not produce correct results on Mac currently.* The issue is in the KLayout DRC checks. The produced GDS are fine.

Then install the CF tools and the design should be ready for tapeout (submit to CF) ;-)

cf init
cf push

Or do a precheck first:

make precheck
DISABLE_LVS=1 make run-precheck

The Leros test case can be run with cocotb:

make cocotb-verify-leros_adder_test-rtl

Refer to README for basic Caravel documentation.

Address Map

Wishbone User space is mapped as follows: 0x3000_0000 - 0x300F_FFFF

Address Range	Description
0x3000_0000 - 0x3000_FFFF	Leros with CF SRAM
0x3001_0000 - 0x3001_FFFF	Leros with OpenRAM SRAM
0x3002_0000 - 0x3002_FFFF	Leros with DFF RAM
0x3003_0000 - 0x3003_FFFF	Leros with RTL Register File
0x3004_0000 - 0x3004_FFFF	Sylvan's Register File
0x3005_0000 - 0x3005_FFFF	Wishbone 6-bit GPIO

GPIO Mapping

Range	Description
37:32	Wishbone 6-bit GPIO
31	HelloMorse
30:25	Leros with OpenRAM SRAM
24:19	Leros with CF SRAM
18:13	Leros with RTL Register File
12:7	Leros with DFF RAM
6:0	Blocked by caravel

The Chip GDS:

The Complete Caravel GDS: