This repository contains the material for the 13-week course 02118 - Introduction to Chip Design at the Technical University of Denmark (DTU). This course was developed with support from the Edu4Chip project.
- Practicalities
- Course Aim
- Reading Material
- Lecture Plan
- Project
- Exam
- Learning Objectives
- License
- Funding
The course runs on Wednesdays from 13:00 to 17:00 in TBD: Building 308 - Room 017.
Each weekly session consist of a lecture and laboratory work. Some session will be fully dedicated to laboratory work (especially at the end of the course when you are expected to work on your project).
The course has two teachers:
Install the LibreLane tools locally or use the server chipdesign1.compute.dtu.dk. The tools are currently usable on Linux and MacOS (even native with Mac Silicon). For Windows use WSL2 to have a Linux environment. There is no official support for Windows available. See Section 1.2 in the Chip Design Booklet for installation instructions.
This course is an introduction to the design of digital integrated circuits. It covers the basics of digital circuits, the tools used, and the process of designing a chip. The course is based open-source tools and open-source PDKs. The course also gives the possibility for student projects to be taped out on Tiny Tapeout.
- Lecture slides and lab material
- The textbook CMOS VLSI Design, A Circuits and Systems Perspective by Neil H. E. Weste and David Harris, also available as PDF
- The Chip Design Booklet is a start of notes and exercises for the course.
- The material related to the open-source tools we use, including installation instructions: LibreLane Documentation
- For a quick start you can explore LibreLane in the browser
- Caravel Documentation
- Chisel Book (as reference when doing designs in Chisel)
This is the list of lectures from 2025. It will be adapted for 2026.
- Overview of chip design and its importance in modern electronics
- Basic terminology and concepts
- Introduction to the LibreLane ASIC design flow
- AISC with standard cells
- PDK
- Local installation of the open-srouce tools (LibreLane)
- Running a "Hello World" example from Verilog source to GDSII
- Explore timing and size
- Explore different reset strategies
- See Section 1.3 in the Chip Design Booklet
- Lecture slides (also available as PDF in DTU-Learn)
- Weste and Harris: 1.1 and 1.12
- OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain
- Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper
- Tiny Tapeout: A Shared Silicon Tapeout Platform Accessible To Everyone
- The need for a controlled switch
- A brief history of the transistor
- The MOSFET transistor
- The NMOS inverter
- The CMOS inverter
- Other gates
- SiliWiz exercises
- See Lab 2 for instructions
- Lecture slides (also available as PDF in DTU-Learn)
- From the textbook:
- 1.3
- 1.4.1, 1.4.2, 1.4.3, 1.4.4, 1.4.5
- 1.5.1, 1.5.2
- 2.1, 2.2*, 2.3*
- quick read, no need to go into details with formulas
- Introduction to standard cells
- Role of standard cells in digital design
- Components of a standard cell library
- Types of standard cells (e.g., logic gates, flip-flops)
- Power, performance, and area
- Characterization of standard cells
- Models and simulation
- Simulate a SkyWater130 standard cell in Spice
- Run your though P&R (OR)
- Handle placement and macro insertion
- Discussion about the project
- Form and register groups in DTU Learn
- Choose a project component to work on (CPU, memory, peripherals, testing, etc.)
- Sign up in the GitHub repository (TBD)
- Details of the LibreLane ASIC design flow
- Individual tools and their outputs
- Caravel
- Tapeout options (CF, waver.space for production, IHP)
- Wishbone bus overview
- Overview of the course project and group formation
- Run steps of the LibreLane flow on a simple design (from Python)
- Explore the different stages of the flow
- Analyze the results and understand the output files
- Harden the Caravel framework with a simple peripheral
- Write a simple Wishbone peripheral (in Chisel)
- Lecture slides (also available as PDF in DTU-Learn)
- LibreLane Documentation
This is a large documentation from which this slide set is based upon, you do not need to read it all. Reference to it when needed.
- Introduction to Verilog
- Introduction to Tiny Tapeout
- Small Verilog example (programmable counter)
- Write a testbench and run it on post-synthesis
- Do it in Chisel and in Verilog
- Do local hardening
- Simulate post-synthesis
- probably need a Verilog or cocotb testbench
- Explore Tiny Tapeout with a Verilog project (GitHub based)
- Use the counters in a memory mapped device (maybe)
- See Lab 4b for instructions
- Work on the project
- Lecture slides (also available as PDF in DTU-Learn)
- Find good Verilog projects and read the code
- E.g., YARVI
- Introduction to verification
- Verification methodologies
- Simulation-based verification
- Testbench design
- Assertions and coverage metrics
- Brief overview of formal verification
- Industry Standards, tools, and frameworks in verification
- Verification lab
- Lecture slides (also available as PDF in DTU-Learn)
- TBA
- TBD
- TBD
- Lecture slides (also available as PDF in DTU-Learn)
-
Memory types and memory organization
-
Register files: FF, sync mem, latches, custom design
-
Memory macros (IP blocks)
-
Memory options with the SkyWater130 PDK
-
Lecture slides TBD
- Exploring memory options with SkyWater130
- Lecture slides (also available as PDF in DTU-Learn)
- Chip design at Demant
- Industrial design and implementation flow overview
- Design and implementation considerations for low power
- Challenges in lower design nodes (and/or at lower voltages)
- Finalise the functional implementation of your project
- Lecture slides - not yet availble
- Chip design rules
- Power distribution design, optimization, and analysis
- Digital design timing
- Clock distribution challenges and clock trees
- Power optimization through clock gating
- Timing closure
- Run routing (OR)
- Fix shorts and design rule violations
- None
The full time slot is dedicated to project work.
- Run Timing closure and LVS
- Fix timing violations and handle design missmatches
- "tape out" your project
Each group presents their finalized project and discusses the results.
- Lecture slides sources
- PDF in DTU Learn (05_Chisel_unit1-4)
- High paced introduction of Chisel
- Lab 1-4 at chisel-lab
- Work on the project
- Lecture slides
- Digital Design with Chisel
- Introduction to Verilog
- Introduction to Tiny Tapeout
- Small Verilog example (programmable counter)
- Write a testbench and run it on post-synthesis
- Do it in Chisel and in Verilog
- Do local hardening
- Simulate post-synthesis
- probably need a Verilog or cocotb testbench
- Explore Tiny Tapeout with a Verilog project (GitHub based)
- Use the counters in a memory mapped device (maybe)
- See Lab 3 for instructions
- Work on the project
- Lecture slides (also available as PDF in DTU-Learn)
- Find good Verilog projects and read the code
- E.g., YARVI
Each group presents their project plan and initial developments. This is a key milestone in the course, where you will receive valuable feedback from the teachers and your peers.
Please prepare a short presentation (a few simple slides) for a maximum duration of 10 minutes. Your presentation should include:
- Objectives: What are the key goals of your project?
- Current actions: What steps have been taken so far?
- Time plan: Timeline for development and key milestones.
- Preliminary design: Initial architecture, block diagrams, ideas, etc.
- Implementation and verification plan: How do you plan to implement and validate your design?
- Obstacles and open matters: Are there any obstacles or current problems that prevent moving forward?
After each presentation, we will have a 5 minutes feedback session.
The schedule of the presentations is announced on DTU-Learn. Please note that all groups should be present for all the presentations.
To make the most of the presentation and feedback session, please take into account the following tips:
- Keep your presentation structured and concise.
- Focus on clarity: explain your choices and reasoning.
- Be prepared to engage with feedback and questions.
- Work on the project
The course project is focused on designing and implementing a System-on-Chip (SoC) using open-source tools. The goal is to collaboratively develop a working SoC that includes a CPU, memory, peripherals, and essential interfaces.
The project is hosted at DTU-SoC-2025.
The project should be carried out in groups of 3 people (groups of 2 are also possible but less preferred). You are free to select your group members. Groups should be registered as soon as formed in the DTU-Learn group forming facility. If you experience difficulties forming a group, please contact the teacher.
When forming a new group, please make sure that you align expectations between the members. To achieve this, we recommend having a discussion about each member’s availability, work habits, and goals for the course to ensure a smooth and collaborative experience.
Each student group will contribute to a part of the SoC. You can choose from the following components:
- Cache system for Wildcat
- Memory controller (handling SPI-based flash, RAM access, memory-mapped peripherals)
- Peripherals:
- VGA character display
- Keyboard interface
- Serial port (UART)
- GPIO and timer
- Special IOs (PWM and others)
- SPI interface (with optional quad-mode support)
- Continuous integration (managing continuous verification after design changes)
- Verification (creating testbenches, simulations, and FPGA testing)
- Physical design tools (OpenLane2 workflow, synthesis, placement, routing, signoff)
- Caravel integration (integrating the design with the Caravel framework)
See Lecture 4 for more details.
To ensure smooth progress, we will coordinate weekly during the lab sessions. These sessions will be used to:
- Discuss progress and challenges faced by each group
- Provide feedback and guidance on design, implementation, and verification
- Address any issues related to tools and integration
- Keep track of milestones and ensure alignment with the tapeout schedule
- Work on the project
You are expected to hand-in a report describing your desing and your work. The report should be formatted as IEEE paper (IEEEtran template) and not be longer than 4 pages. In the following, you can find the expected content of the report (not all entries may apply to your project):
- Title
- Group number
- Names and student IDs of the group members
- Contributions: Clearly state what each team member contributed to the project. This section is crucial for evaluating individual contributions and ensuring fair grading.
- Introduction: Introduce your chosen design, outlining its purpose, objectives, and specifications.
- Design: Summarize the key aspects of your design, including its functionality and features. Provide a detailed block diagram to illustrate the overall architecture. Explain how the design fits into the larger system.
- Implementation:
- Describe how you implemented your design using Verilog, Chisel, or both.
- Highlight specific steps in the chip design process and explain how open-source tools were used.
- Include details on performance, and area and any challenges encountered during the implementation.
- Explain the testing methodology, including simulation results.
- Describe how you verified the design.
- Include results from DRC (Design Rule Check), timing analysis, etc. to demonstrate the design's readiness for tapeout.
- Tapeout preparation: Summarize the final steps taken to prepare the design for tapeout, (integration with the Caravel framework and/or and ensuring compliance with Tiny Tapeout requirements).
- Link/explanantion where to find your code Explain where your code is located in your repository. Possibly link to a README file that includes all needed technical instructions.
The deadline for the hand-in is the 4th of May 2025 at 23:59.
- Relevance and complexity
- Does the design address a meaningful challenge?
- Correctness
- Does the implementation function as intended?
- Are there any critical design flaws?
- Optimization
- Area and performance efficiency considerations
- Power consumption and design trade-offs
- Verification quality
- Comprehensive testbenches and accurate simulations
- Pre-synthesis and post-synthesis validation
- Testing quality
- Functional FPGA testing
- DRC and layout verification
- Completion
- Is the design ready for tapeout?
- Report quality
- Clear documentation of methodology, challenges, and results
- Week 4: Form groups, select project, open discussion
- Week 6: Finalize desing concept, define specs, align between groups
- Weeks 7-9: Develop design, run simulations
- Weeks 10-11: Initiate physical design, P&R, Problem strategies
- Weeks 12-13: Finalize physical design, complete DRC/LVS checks, prepare for submission
Project report and presentation.
All original content in this repository, including text, code, and other materials, is licensed under the CC0 1.0 Universal license (see LICENSE file), unless otherwise noted.
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Funded by the European Union within the Edu4Chip - Joint Education for Advanced Chip Design in Europe project. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or European Health and Digital Executive Agency (HaDEA). Neither the European Union nor the granting authority can be held responsible for them.
