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42 changes: 17 additions & 25 deletions Cargo.lock

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12 changes: 6 additions & 6 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ colored = { version = "2.0", default-features = false }
convert_case = { version = "0.4", default-features = false }
corncobs = { version = "0.1.1", default-features = false }
cortex-m = { version = "0.7", default-features = false, features = ["inline-asm"]}
cortex-m-rt = { version = "0.6.12", default-features = false }
cortex-m-rt = { version = "0.7.5", default-features = false }
cortex-m-semihosting = { version = "0.5.0", default-features = false }
crc = { version = "3.0.0", default-features = false }
critical-section = { version = "1.1.2" }
Expand All @@ -89,7 +89,7 @@ indexmap = { version = "1.4.0", default-features = false, features = ["serde-1"]
indoc = { version = "2.0.3", default-features = false }
itertools = { version = "0.10.5", default-features = false }
leb128 = { version = "0.2.5", default-features = false }
lpc55-pac = { version = "0.4", default-features = false }
lpc55-pac = { version = "0.5", default-features = false }
memchr = { version = "2.4", default-features = false }
memoffset = { version = "0.6.5", default-features = false }
minicbor = { version = "2.1.1", default-features = false }
Expand Down Expand Up @@ -127,10 +127,10 @@ ssh-key = { version = "0.6.6", default-features = false, features = ["std", "p25
spin = { version = "0.9.4", default-features = false, features = ["mutex", "spin_mutex"]}
ssmarshal = { version = "1.0.0", default-features = false }
static_assertions = { version = "1", default-features = false }
stm32f3 = { version = "0.13.0", default-features = false }
stm32f4 = { version = "0.13.0", default-features = false }
stm32h7 = { version = "0.14", default-features = false }
stm32g0 = { version = "0.15.1", default-features = false }
stm32f3 = { version = "0.15", default-features = false }
stm32f4 = { version = "0.15", default-features = false }
stm32h7 = { version = "0.15", default-features = false }
stm32g0 = { version = "0.15", default-features = false }
strsim = { version = "0.10.0", default-features = false }
syn = { version = "2", default-features = false, features = ["derive", "parsing", "proc-macro", "extra-traits", "full", "printing"] }
toml = { version = "0.9.6", default-features = false, features = ["parse", "display", "serde", "preserve_order"] }
Expand Down
4 changes: 2 additions & 2 deletions app/cosmo/base.toml
Original file line number Diff line number Diff line change
Expand Up @@ -1389,7 +1389,7 @@ input = {port = "B", pin = 14, af = 5}
[config.spi.spi2.devices.spartan7_fpga]
mux = "port_b"
cs = []
clock_divider = "DIV8" # 12.5 MHz
clock_divider = "Div8" # 12.5 MHz
# no CS pin; we're using the SPI peripheral to send synchronized CLK + DATA

# SPI_SP_TO_KSZ8463_SCK
Expand Down Expand Up @@ -1444,7 +1444,7 @@ input = {port = "J", pin = 11, af = 5}
[config.spi.spi5.devices.rot]
mux = "port_j"
cs = [{port = "K", pin = 1}]
clock_divider = "DIV256"
clock_divider = "Div256"

################################################################################

Expand Down
2 changes: 1 addition & 1 deletion app/demo-stm32h7-nucleo/app-h743.toml
Original file line number Diff line number Diff line change
Expand Up @@ -185,7 +185,7 @@ input = {port = "A", pin = 6, af = 5} # miso
[config.spi.spi1.devices.pins]
mux = "cn7_arduino"
cs = [{port = "D", pin = 14}]
clock_divider = "DIV16"
clock_divider = "Div16"


[config.net]
Expand Down
2 changes: 1 addition & 1 deletion app/demo-stm32h7-nucleo/app-h753.toml
Original file line number Diff line number Diff line change
Expand Up @@ -233,7 +233,7 @@ input = {port = "A", pin = 6, af = 5}
[config.spi.spi1.devices.pins]
mux = "cn7_arduino"
cs = [{port = "D", pin = 14}]
clock_divider = "DIV32"
clock_divider = "Div32"

[config.net]
# UDP ports in sockets below are assigned in oxidecomputer/oana
Expand Down
2 changes: 1 addition & 1 deletion app/gemini-bu/app.toml
Original file line number Diff line number Diff line change
Expand Up @@ -321,4 +321,4 @@ input = {port = "E", pin = 5, af = 5}
[config.spi.spi4.devices.rot]
mux = "port_e"
cs = [{port = "E", pin = 4}]
clock_divider = "DIV256"
clock_divider = "Div256"
2 changes: 1 addition & 1 deletion app/gimlet/base.toml
Original file line number Diff line number Diff line change
Expand Up @@ -1288,7 +1288,7 @@ input = {port = "E", pin = 5, af = 5}
[config.spi.spi4.devices.rot]
mux = "rot"
cs = [{port = "E", pin = 4}]
clock_divider = "DIV256"
clock_divider = "Div256"

# VLAN configuration
[config.net.vlans.sidecar1]
Expand Down
18 changes: 9 additions & 9 deletions app/gimlet/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -137,8 +137,8 @@ fn system_init() {
// the prescaler.
divm: 1,
// VCO must tolerate an 8MHz input range:
vcosel: device::rcc::pllcfgr::PLL1VCOSEL_A::WIDEVCO,
pllrange: device::rcc::pllcfgr::PLL1RGE_A::RANGE8,
vcosel: device::rcc::pllcfgr::PLL1VCOSEL_A::WideVco,
pllrange: device::rcc::pllcfgr::PLL1RGE_A::Range8,
// DIVN governs the multiplication of the VCO input frequency to produce
// the intermediate frequency. We want an IF of 800MHz, or a
// multiplication of 100x.
Expand All @@ -148,23 +148,23 @@ fn system_init() {
divn: 100 - 1,
// P is the divisor from the VCO IF to the system frequency. We want
// 400MHz, so:
divp: device::rcc::pll1divr::DIVP1_A::DIV2,
divp: device::rcc::pll1divr::DIVP1_A::Div2,
// Q produces kernel clocks; we set it to 200MHz:
divq: 4 - 1,
// R is mostly used by the trace unit and we leave it fast:
divr: 2 - 1,

// We run the CPU at the full core rate of 400MHz:
cpu_div: device::rcc::d1cfgr::D1CPRE_A::DIV1,
cpu_div: device::rcc::d1cfgr::D1CPRE_A::Div1,
// We down-shift the AHB by a factor of 2, to 200MHz, to meet its
// constraints:
ahb_div: device::rcc::d1cfgr::HPRE_A::DIV2,
ahb_div: device::rcc::d1cfgr::HPRE_A::Div2,
// We configure all APB for 100MHz. These are relative to the AHB
// frequency.
apb1_div: device::rcc::d2cfgr::D2PPRE1_A::DIV2,
apb2_div: device::rcc::d2cfgr::D2PPRE2_A::DIV2,
apb3_div: device::rcc::d1cfgr::D1PPRE_A::DIV2,
apb4_div: device::rcc::d3cfgr::D3PPRE_A::DIV2,
apb1_div: device::rcc::d2cfgr::D2PPRE1_A::Div2,
apb2_div: device::rcc::d2cfgr::D2PPRE2_A::Div2,
apb3_div: device::rcc::d1cfgr::D1PPRE_A::Div2,
apb4_div: device::rcc::d3cfgr::D3PPRE_A::Div2,

// Flash runs at 200MHz: 2WS, 2 programming cycles. See reference manual
// Table 13.
Expand Down
4 changes: 2 additions & 2 deletions app/gimletlet/base-gimletlet2.toml
Original file line number Diff line number Diff line change
Expand Up @@ -176,8 +176,8 @@ input = {port = "C", pin = 11, af = 6}
[config.spi.spi3.devices.spi3_header]
mux = "port_c"
cs = [{port = "A", pin = 15}]
clock_divider = "DIV256" # 774 kHz, works with LPC55 clock at 48MHz
# clock_divider = "DIV128" # 1.5 MHz, fails unless LPC55 clock is at 96MHz
clock_divider = "Div256" # 774 kHz, works with LPC55 clock at 48MHz
# clock_divider = "Div128" # 1.5 MHz, fails unless LPC55 clock is at 96MHz

[config.spi.spi4]
controller = 4
Expand Down
4 changes: 2 additions & 2 deletions app/grapefruit/base.toml
Original file line number Diff line number Diff line change
Expand Up @@ -428,7 +428,7 @@ input = {port = "B", pin = 14, af = 5} # not actually used in FPGA config
[config.spi.spi2.devices.spartan7_fpga]
mux = "port_b"
cs = []
clock_divider = "DIV8" # 12.5 MHz
clock_divider = "Div8" # 12.5 MHz
# no CS pin; we're using the SPI peripheral to send synchronized CLK + DATA

[config.spi.spi4]
Expand All @@ -443,7 +443,7 @@ input = {port = "E", pin = 5, af = 5}
[config.spi.spi4.devices.rot]
mux = "port_e"
cs = [{port = "E", pin = 4}]
clock_divider = "DIV256"
clock_divider = "Div256"

################################################################################

Expand Down
2 changes: 1 addition & 1 deletion app/minibar/app.toml
Original file line number Diff line number Diff line change
Expand Up @@ -315,7 +315,7 @@ controller = 4
[config.spi.spi4.devices.rot]
mux = "rot"
cs = [{port = "E", pin = 4}]
clock_divider = "DIV256"
clock_divider = "Div256"

[config.spi.spi4.mux_options.rot]
outputs = [
Expand Down
2 changes: 1 addition & 1 deletion app/psc/base.toml
Original file line number Diff line number Diff line change
Expand Up @@ -526,7 +526,7 @@ input = {port = "E", pin = 5, af = 5}
[config.spi.spi4.devices.rot]
mux = "rot"
cs = [{port = "E", pin = 4}]
clock_divider = "DIV256"
clock_divider = "Div256"

# VLAN configuration
[config.net.vlans.sidecar1]
Expand Down
2 changes: 1 addition & 1 deletion app/sidecar/base.toml
Original file line number Diff line number Diff line change
Expand Up @@ -1114,7 +1114,7 @@ controller = 4
[config.spi.spi4.devices.rot]
mux = "rot"
cs = [{port = "E", pin = 4}]
clock_divider = "DIV256"
clock_divider = "Div256"

[config.spi.spi4.mux_options.rot]
outputs = [
Expand Down
21 changes: 11 additions & 10 deletions build/spi/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -85,23 +85,24 @@ pub struct DeviceDescriptorConfig {
pub cs: Vec<GpioPinConfig>,
}

// N.B. the names in this enum _must_ match those used in the PAC!
#[derive(Copy, Clone, Debug, Deserialize)]
pub enum ClockDivider {
DIV2,
DIV4,
DIV8,
DIV16,
DIV32,
DIV64,
DIV128,
DIV256,
Div2,
Div4,
Div8,
Div16,
Div32,
Div64,
Div128,
Div256,
}

impl Default for ClockDivider {
fn default() -> ClockDivider {
// When this config mechanism was introduced, we had everything set at
// DIV64 for a ~1.5625 MHz SCK rate.
Self::DIV64
// Div64 for a ~1.5625 MHz SCK rate.
Self::Div64
}
}

Expand Down
22 changes: 9 additions & 13 deletions drv/spi-api/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -17,21 +17,17 @@ fn main() -> Result<()> {
let dest_path = out_dir.join("spi_devices.rs");
let mut file = File::create(dest_path)?;

if let Ok(global_config) = build_util::config::<SpiGlobalConfig>() {
writeln!(&mut file, "pub mod devices {{")?;
for (periph, p) in global_config.spi {
writeln!(
&mut file,
" // {periph} ({} devices)",
p.devices.len()
)?;
for (i, name) in p.devices.keys().enumerate() {
let name = name.to_uppercase();
writeln!(&mut file, " pub const {name}: u8 = {i};")?;
}
let global_config = build_util::config::<SpiGlobalConfig>()?;
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praise: Wow, this would've probably been a really confusing bug: build succeeds but devices are somehow missing from the output?


writeln!(&mut file, "pub mod devices {{")?;
for (periph, p) in global_config.spi {
writeln!(&mut file, " // {periph} ({} devices)", p.devices.len())?;
for (i, name) in p.devices.keys().enumerate() {
let name = name.to_uppercase();
writeln!(&mut file, " pub const {name}: u8 = {i};")?;
}
writeln!(&mut file, "}}")?;
}
writeln!(&mut file, "}}")?;

Ok(())
}
1 change: 0 additions & 1 deletion drv/sprot-api/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,6 @@ counters = { path = "../../lib/counters" }
derive-idol-err = { path = "../../lib/derive-idol-err" }
drv-caboose = { path = "../../drv/caboose" }
drv-lpc55-update-api = { path = "../../drv/lpc55-update-api" }
drv-spi-api = { path = "../../drv/spi-api" }
drv-update-api = { path = "../../drv/update-api" }
dumper-api = { path = "../../task/dumper-api" }
ringbuf = { path = "../../lib/ringbuf" }
Expand Down
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