Rebase main onto QEMU master - #10
Draft
github-actions[bot] wants to merge 6804 commits into
Draft
Conversation
connorc0405
marked this pull request as draft
March 18, 2025 17:33
lacraig2
force-pushed
the
main
branch
3 times, most recently
from
April 8, 2025 18:24
8b2d81e to
b705830
Compare
lacraig2
force-pushed
the
main
branch
3 times, most recently
from
April 25, 2025 20:10
9ed05e4 to
ff8c829
Compare
lacraig2
force-pushed
the
main
branch
2 times, most recently
from
May 18, 2025 18:54
e3cd32c to
1db5aa4
Compare
lacraig2
force-pushed
the
main
branch
2 times, most recently
from
July 24, 2025 14:02
b6fd054 to
1152790
Compare
lacraig2
force-pushed
the
main
branch
3 times, most recently
from
August 15, 2025 17:58
1e3e01c to
b9e95c6
Compare
Add the following new instructions in LoongArch v1.1: - frecipe.s - frecipe.d - frsqrte.s - frsqrte.d - vfrecipe.s - vfrecipe.d - vfrsqrte.s - vfrsqrte.d - xvfrecipe.s - xvfrecipe.d - xvfrsqrte.s - xvfrsqrte.d They are guarded by CPUCFG2.FRECIPE. Altought the instructions allow implementation to improve performance by reducing precision, we use the existing softfloat implementation. Signed-off-by: Jiajie Chen <c@jia.je> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Add the following instructions in LoongArch v1.1: - llacq.w - screl.w - llacq.d - screl.d They are guarded by CPUCFG2.LLACQ_SCREL. Signed-off-by: Jiajie Chen <c@jia.je> Co-developed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Add the sc.q instruction in LoongArch v1.1, guarded by CPUCFG2.SCQ. It is implemented by reading 128bit data (llval + llval_high) in ll.d when aligned to 16B boundary, and cmpxchg 128bit in sc.q. If ld.d matches the higher part of the 128bit, its data is taken from llval_high. Expected assembly sequence: ll.d lo, base, 0 ld.d hi, base, 8 sc.q lo, hi, base Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Add LA v1.1 new instructinos to max cpu by enabling new features in CPUCFG2. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
…into staging Various patches related to single binary effort: - Reduce RISC-V Boston tests - Prohibit target_ulong / TARGET_PAGE_SIZE uses on s390x target - Build target/arm/arm-qmp-cmds once - Forbid legacy native endianness & ld/st_phys APIs on SPARC targets - Forbid legacy ld/st_phys APIs on x86 targets - Rename OpenRISC -> or1k - Avoid QAPI parsing in target_arch() # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmmKO5wACgkQ4+MsLN6t # wN5EchAAxWVK1eWW5cO7R3+PxWFFzAMcyTzVUftNIyMLZQcXg5C6P2MSt8gsU8KC # oOwl9S85u5dYh/PlAJtQYC+wtNUxawaJk26vUm3k+uOY2XgqCLtFKts+id15F3Hb # RueLTEM095jbFgl5OzDwFVRAXP/z727vRsSN2ULXdphHpSVnrROGLz++Uqn7wAmd # S9u8q35VVRkHl5TRQBDCYNddvGkW6PY0lSdDPhPMYFDH0Pln1Ao3fEn1zfa1c2gP # HQ1d4MdHi8XX041o2TPFZf74tEs0EeSaxBtfyFEMByOs2kVe8oiX5oaM37vbejLa # WAfwkG1imw9LcMo0VyjMGgQMb0tkdCVJWzp47eEAEhxSHBsfX5w7+jG0pBng3BBJ # 6BrcfzVcWeqScUJPdXbM+mY+uBW09JHsTH37aM1NCsRlJI3gys2TfY/oIyVb7aqM # C17DPKwxv+LVC5BI8LPAkh/nM2/sh5jtC+DjqaAFfAlo3JPLIUOcEIpFikiGbbzU # MFH1k6YRAee3e7fW1Sw26R17Sf+VTYO9EhYiyWdyAIaBPZ5r7V/fVZWNNrBvh3Zd # +ETHyRr/mwxbPx3fiNRg880jsP6mVhpLqykRJN1ttW0eQPaA96aqLmDrez/NFF4D # NisJI8nlJNSEnF84cKgpV74mbIM5lmwMQi684rnI/Ty31X1hLxU= # =dY6o # -----END PGP SIGNATURE----- # gpg: Signature made Mon Feb 9 19:55:08 2026 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'single-binary-20260206' of https://github.com/philmd/qemu: (30 commits) target-info: Statically initialize target_arch meson: Add TARGET_ARCH to config_target_data qapi: Add hexagon to SysEmuTarget hw/or1k: Rename or1k-sim.c from openrisc_sim.c docs/system/or1k: Rename from openrisc tests/tcg/or1k: Rename from openrisc hw/or1k: Rename from openrisc include/hw/or1k: Rename from openrisc target/or1k: Rename from openrisc configs/targets: Restrict the legacy ldst_phys() API on x86 targets hw/intc/ioapic: Replace legacy st_phys() -> address_space_st() hw/intc: Mark x86-specific [IO]APIC peripherals as little-endian target/i386: Use explicit little-endian LD/ST API configs/targets: Restrict legacy ldst_phys() API on 32-bit SPARC target target/sparc: Replace legacy st_phys() -> address_space_st() configs/targets: Forbid SPARC to use legacy native endianness APIs target/sparc: Replace MO_TE -> MO_BE target/sparc: Remove dubious swapping in LD_code() helper target/arm/arm-qmp-cmds.c: make compilation unit common target/s390x: Expand tcg_global_mem_new() -> tcg_global_mem_new_i64() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
…qemu into staging pull-loongarch-2026-02-10 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQTKRzxE1qCcGJoZP81FK5aFKyaCFgUCaYqcuAAKCRBFK5aFKyaC # FkgeA/9G0mHfS7GOrna5V3mUkTmCZt0vDRyhoUvQYhq5xOxiw6xTwUHSnUGhrW1X # Rl5I7TcRiv/Bl6pmDB3c0lZ4+V70MQBufxpwURA3XzKT1C2RSjVHEr7p2WzRiXPF # 0Zgam8cG2xugT3Al9gdsrba1br/OLXtJHj1+n/L6tgAI8V2Beg== # =WO9M # -----END PGP SIGNATURE----- # gpg: Signature made Tue Feb 10 02:49:28 2026 GMT # gpg: using RSA key CA473C44D6A09C189A193FCD452B96852B268216 # gpg: Good signature from "Song Gao <gaosong@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CA47 3C44 D6A0 9C18 9A19 3FCD 452B 9685 2B26 8216 * tag 'pull-loongarch-20260210' of https://github.com/gaosong715/qemu: target/loongarch: Add LA v1.1 instructions to max cpu target/loongarch: Add sc.q instructions target/loongarch: Add llacq/screl instructions target/loongarch: Add estimated reciprocal instructions target/loongarch: Add amcas[_db].{b/h/w/d} target/loongarch: Add am{swap/add}[_db].{b/h} target/loongarch: Require atomics to be aligned Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
lacraig2
force-pushed
the
main
branch
2 times, most recently
from
February 11, 2026 15:28
fa5d3c1 to
57d6a84
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
20 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
No description provided.