HuC6260

The HuC6260 is the Video Color Encoder (VCE), referred to as 鉄観音 - "TETSU" by NEC-HE.

The Video Color Encoder (VCE) basically supplies the picture on your television.

It is connected to the HuC6280 and the
HuC6270. The HuC6280
provides palettes and can modify a few settings while the
HuC6270 provides a data stream to which it applies
the palettes.

Notes:

• All mentions of "dot" have been replaced with "pixel" (DCC is now PCC).
• All registers are 16 bit.

Interface

Needs verification

Pins	Function	Input/Output	Connection
A0 - A2	Register Selection	Input	A0 - A2 from CPU
[o]RD[/o]	Activate read from register	Input	[o]RD[/o] from CPU
[o]WR[/o]	Activate write to register	Input	[o]WR[/o] from CPU
D0 - D7	Data bus for registers	Input / Output	D0 - D7 from CPU
VD0 - VD8		Input / Output	VD0 - VD7, SPBG from VDC
[o]HSYNC[/o]	Horizontal Synchronization	Input / Output	[o]HSYNC[/o] from VDC
[o]VSYNC[/o]	Vertical Synchronization	Input / Output	[o]VSYNC[/o] from VDC

Registers

$0400 - CR - Control Register

Write only register.

Bit(s)	Description	Values
0 - 1	PCC - Pixel Clock Control	00 = 5.3693175 MHz[br] 01 = 7.15909 MHz[br] 10 = 10.738635 MHz[br] 11 = 10.738635 MHz
2	Frame/Field Configuration	0 = 262-line frame[br] 1 = 263-line frame
3 - 6	???	???
7	Strip Colorburst	0 = Colorburst intact[br] 1 = Strip colorburst
8 - 15	(unused)

$0402 - CTA - Color Table Address Register

Write only register.

Bit(s)	Description	Values
0 - 8	index for the color table	0 to 511
9 - 15	(unused)

Note: This register is auto-incremented after each access to the color data register.

$0404 - CTW - Color Table Write Register / CTR - Color Table Read Register

Write/Read register.

Access (read/write) to this register causes CTA register to increment.

Bit(s)	Description
0 - 2	Blue
3 - 5	Red
6 - 8	Green
9 - 15	(unused)

Notes

Display artifact[br] When bit 2 of $0400 is set, a flip-flop is toggled once per frame that offsets the entire frame by one pixel. I'll call this the pixel shift state. Depending on the last state of the flip-flop when bit 2 of $0400 is reset, the pixel shift state can be forced to zero or one. When enabled this completely eliminates the color fringe artifact (chromatic aberration) that is apparent for PCC settings $00-$03.

The VCE applies a 1/2 pixel shift on every even or odd scanline. The selection of even or odd scanlines is inverted on every frame, and is further inverted by the pixel shift state, however in all but 2 settings this is unnoticable.

In "C" pseudocode these work like so:

[code]

//each frame
if(dcc & 4) pixelShiftState ^= 1;
//each scanline
halfPixelShiftState = (framecount & 1) ^ (scanline & 1) ^ (pixelShiftState & 1);

[/code]

Here are the results of some tests I did when the screen is filled with alternating white and black pixels on even scanlines and black and white pixels on odd scanlines.

This is a worst-case test pattern for observing artifacting (note that artifacting only affects composite and RF output not RGB)

PCC	Effect
$00	There is a repeating pattern of pink and green columns across the display. Depending on the pixel shift state, the color order is reversed (pink, green, pink.. or green, pink, green...).
$01	The entire screen is filled with what appears as solid orange or sky blue depending on the pixel shift state.
$02	Same as $00, except for the columns are thinner due to the increased resolution.
$03	Same as $02. In this mode the half pixel shift state is not selected by the frame count anymore, just by the scanline LSB and pixel shift state. If you toggle the pixel shift state you can control if the even or odd lines have a half pixel offset. This causes a highly visible skew between pairs of scanlines due to the horizontal offset every one of two scanlines has.
$04	The rainbow pattern alternates at 30 Hz between pink and green. The result is a mostly white area.
$05	The entire screen alternates at 30 Hz between orange and sky blue. It is horrible to look at.
$06	Same as $00, except for the columns are thinner due to the increased resolution. The columns appear to move horizontally across the screen due to their positions changing at 30 Hz.
$07	Same as $06. Because the pixel shift state is being toggled, the skew is almost not noticeable.

For settings that give a 7.15909 MHz pixel clock ($01 and $05), the pixel rate is exactly twice of the color subcarrier frequency (3.579545 MHz). I think this is what causing alternating pixels to appear as a single color rather than two distinct ones.

Pin assignments

Pinout diagram for the HuC6260.
Circuit diagram for the HuC6260.

Pin	Signal	Direction	Description
1		N/A	Not Connected
2	XIN	in	21.477270 MHz clock input (OSC)
3	GND	s	Ground
4	D8	in / out	Data bus, bit 8 / Not Connected!
5	D7	in / out	Data bus, bit 7
6	D6	in / out	Data bus, bit 6
7	D5	in / out	Data bus, bit 5
8	D4	in / out	Data bus, bit 4
9	D3	in / out	Data bus, bit 3
10	D2	in / out	Data bus, bit 2
11	D1	in / out	Data bus, bit 1
12	D0	in / out	Data bus, bit 0
13		N/A	Not Connected
14		N/A	Not Connected
15		N/A	Not Connected
16		N/A	Not Connected
17	BRT-	out
18	BRTC	out
19		N/A	Not Connected
20	BURS
21		N/A	Not Connected
22	BRT+	out
23	B-Y-	out
24	B-YC	out
25		N/A	Not Connected
26	B-Y	out
27		N/A	Not Connected
28	B-Y+	out
29		N/A	Not Connected
30	R-Y+	out
31	R-YC	out
32		N/A	Not Connected
33	R-Y	out
34		N/A	Not Connected
35	R-Y+	out
36		N/A	Not Connected
37	Y-	out
38	YC	out
39		N/A	Not Connected
40	Y	out
41		N/A	Not Connected
42	Y+	out
43	SYN-	out
44	SYNC	out
45	SYN+	out
46	RGB-	out
47	VIDEO G	out
48		N/A	Not Connected
49	VIDEO R	out
50		N/A	Not Connected
51	VIDEO R	out
52	RGB+	out
53		N/A	Not Connected
54		N/A	Not Connected
55		N/A	Not Connected
56		N/A	Not Connected
57		N/A	Not Connected
58		N/A	Not Connected
59		N/A	Not Connected
60		N/A	Not Connected
61	SEL
62	VD0	in / out
63	VD1	in / out
64	VD2	in / out
65	VD3	in / out
66	VD4	in / out
67	VD5	in / out
68	VD6	in / out
69	VD7	in / out
70	VD8	in / out
71	HSYN	in / out
72	VSYN	in / out
73	CK	out
74	A0	in
75	A1	in
76	A2	in
77	[o]WR[/o]	in
78	[o]CS[/o]	in
79		N/A	Not Connected
80	8/[o]16[/o]	in

Patents

Patent for VCE

Patent for VCE/VDC