Chimera: A Flexible Multi-Accelerator Framework for Heterogeneous SoC Integration

Chimera is an open-source, highly configurable microcontroller System-on-Chip (SoC) template designed for multi-cluster, heterogeneous computing systems. Its primary objective is to provide a modular platform for seamlessly integrating and managing hardware accelerators, offering developers and researchers an intuitive and extensible foundation.
Chimera is developed as part of the PULP (Parallel Ultra-Low Power) Platform, a joint effort between ETH Zurich and the University of Bologna.

Getting started Build RTL Platform Simulation Formatting

📜 License

Unless specified otherwise in the respective file headers, all code in this repository is released under permissive licenses.

• Hardware sources and tool scripts are licensed under the Solderpad Hardware License 0.51 (see LICENSE-SHL) or compatible licenses.
• Register file code (e.g. hw/regs/*.sv) is generated using a fork of lowRISC's regtool and is licensed under Apache 2.0 (see LICENSE-APACHE).
• All software sources are licensed under Apache 2.0.

🚀 Getting started

Environment setup for IIS-members

For IIS members, set up the environment by sourcing the iis-env.sh script:

source iis-env.sh

Environment for non IIS-members

Non-IIS users need to follow a few more steps to set up the environment properly.

Bender

Chimera uses Bender to manage hardware dependencies and automatically generate compilation scripts.

Python environment

Python 3.11 or later is required. Create and activate a virtual environment:

make python-venv
source .venv/bin/activate

You can override the Python version using the BASE_PYTHON environment variable. Dependencies are listed in requirements.txt and handled via the python-venv target.

Toolchain

Chimera requires a working RISC-V GCC toolchain for building the Cheshire 32-bit host code. Follow the Installation (Newlib) instructions from pulp-platform/riscv-gni-toolchain.
After installation, export the toolchain path:

export RISCV_GCC_BINROOT=/path/to/gcc/bin
export $PATH=$PATH:$RISCV_GCC_BINROOT

To verify that the toolchain is in your path:

which riscv32-unknown-elf-gcc

🛠️ Build RTL

If you have all needed dependencies and you want to build the full Chimera SoC, both RTL and SW, run:

make chim-all

Or for more selective builds:

make chw-hw-init
make snitch-hw-init
make chim-sw
make chim-bootrom-init

⚠️ You must build the software (chim-sw) before building the boot ROM (chim-bootrom-init).

Compile Software Tests

To compile the software for Cheshire:

make chim-sw

Platform simulation

To run simulations, ensure you have Questa installed and accessible via vsim (which vsim).
To compile the hardware run make chim-sim.
To run a simulation, use the chim-run target. You must specify the path to the compiled Cheshire binary using the BINARY variable:

make chim-run-batch BINARY=path/to/sw/tests.elf

To run the simulation in batch mode, use the chim-run-batch target.

Additional Help

To list all available make targets and their descriptions:

make help

🧼 Formatting

Verilog Formatting

To format all hardware source files:

verible-verilog-format --flagfile .verilog_format --inplace --verbose hw/*.sv target/sim/src/*.sv

CXX Formatting

To format all files in the sw/ directory, run

python scripts/run_clang_format.py -ir sw/

Our CI uses llvm-12 for clang-format. On IIS machines, run:

python scripts/run_clang_format.py -ir sw/ --clang-format-executable=/usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang-format

python scripts/run_clang_format.py -ir hw/ --clang-format-executable=/usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang-format

If you're not using the IIS setup, specify a valid clang-format-12 binary instead.