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Add synchronous clear #42

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1b5e9b5
Added synchronous clear for fault recovery setback.
Feb 28, 2024
2db198d
[WIP] - Cleaning up synchronous clear integration.
Mar 5, 2024
2027c60
[WIP - 2] - Cleaning up synchronous clear integration.
Mar 13, 2024
5382b10
[WIP - 3] - Cleaning up synchronous clear integration.
Mar 14, 2024
597f271
[WIP - 4] - Cleaning up synchronous clear integration.
May 8, 2024
c253363
Bump common_cells
May 9, 2024
4fc35d7
Add FF with clear.
May 9, 2024
5abe28c
Fix error in hpdcache IF adapter.
May 9, 2024
2254f5c
Better propagate clear_i.
May 9, 2024
e3d38d3
Fix missing comma.
May 9, 2024
6bdb11c
Propagate clear.
May 9, 2024
77c40cd
Fix reset connection.
May 9, 2024
ff5f435
Fix FF in clic controller.
May 9, 2024
a383476
Fix lint.
May 11, 2024
dd633f8
[WIP - 5] - Cleaning up synchronous clear integration.
May 12, 2024
2fdd7c0
Clear all BTB and BHT entries.
May 12, 2024
e485947
Missing comma in miss handler FFARNC.
May 12, 2024
098de6a
Assign default mask value in CSRs regfile.
May 12, 2024
82655fc
GLORIOUS FIX.
May 12, 2024
5f61783
Connect clear in serdiv.
May 12, 2024
cb69af5
Try fix verible-verilog-format.
May 12, 2024
0a27bcf
Try fix lint...
May 12, 2024
a089bd7
Try fix lint...
May 12, 2024
c423efc
Try fix enum assign.
May 13, 2024
2f0d702
Use clearable FF for microarchitectural reset.
May 16, 2024
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2 changes: 1 addition & 1 deletion Bender.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ package:
dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 }
common_cells:
{ git: "https://github.com/pulp-platform/common_cells", version: 1.23.0 }
{ git: "https://github.com/pulp-platform/common_cells", version: 1.35.0 }
fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.1 }
tech_cells_generic:
{ git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
Expand Down
2 changes: 1 addition & 1 deletion common/local/util/sram_pulp.sv
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Expand Up @@ -25,7 +25,7 @@ module sram #(
parameter USER_WIDTH = 1,
parameter USER_EN = 0,
parameter NUM_WORDS = 1024,
parameter SIM_INIT = "none",
parameter SIM_INIT = "zeros",
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@niwis niwis Mar 4, 2024

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Is this necessary?

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@yvantor yvantor Mar 4, 2024

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It is not strictly needed for this PR, no. I swapped this when working on lockstepped redundant execution. In that case if the caches or any memories propagate Xs to the checker that controls the buses, it might have unwanted behaviour (also during RTL simulation). Since memory macros never have undefined states (would be either initialized at random values or at 0), to reproduce a scenario that is more similar to what we would have on the silicon I changed the init parameter. We could do this also in other ways (preloading in testbenches) or anyway remove this from this PR.

parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2)
)(
input logic clk_i,
Expand Down
19 changes: 12 additions & 7 deletions core/ariane_regfile_ff.sv
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Expand Up @@ -31,6 +31,7 @@ module ariane_regfile #(
// clock and reset
input logic clk_i,
input logic rst_ni,
input logic clear_i,
// disable clock gates for testing
input logic test_en_i,
// read port
Expand Down Expand Up @@ -63,14 +64,18 @@ module ariane_regfile #(
if (~rst_ni) begin
mem <= '{default: '0};
end else begin
for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
for (int unsigned i = 0; i < NUM_WORDS; i++) begin
if (we_dec[j][i]) begin
mem[i] <= wdata_i[j];
if (clear_i) begin
mem <= '{default: '0};
end else begin
for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
for (int unsigned i = 0; i < NUM_WORDS; i++) begin
if (we_dec[j][i]) begin
mem[i] <= wdata_i[j];
end
end
if (ZERO_REG_ZERO) begin
mem[0] <= '0;
end
end
if (ZERO_REG_ZERO) begin
mem[0] <= '0;
end
end
end
Expand Down
14 changes: 4 additions & 10 deletions core/axi_shim.sv
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Expand Up @@ -18,6 +18,7 @@
*
*/

`include "common_cells/registers.svh"

module axi_shim #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
Expand All @@ -27,6 +28,7 @@ module axi_shim #(
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic clear_i, // Synchronous clear active high
// read channel
// request
input logic rd_req_i,
Expand Down Expand Up @@ -283,16 +285,8 @@ module axi_shim #(
// ----------------
// Registers
// ----------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
// start in flushing state and initialize the memory
wr_state_q <= IDLE;
wr_cnt_q <= '0;
end else begin
wr_state_q <= wr_state_d;
wr_cnt_q <= wr_cnt_d;
end
end
`FFARNC(wr_state_q, wr_state_d, clear_i, IDLE, clk_i, rst_ni)
`FFARNC(wr_cnt_q, wr_cnt_d, clear_i, '0, clk_i, rst_ni)

// ----------------
// Assertions
Expand Down
38 changes: 13 additions & 25 deletions core/cache_subsystem/axi_adapter.sv
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Expand Up @@ -16,6 +16,8 @@
*/
//import std_cache_pkg::*;

`include "common_cells/registers.svh"

module axi_adapter #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned DATA_WIDTH = 256,
Expand All @@ -24,9 +26,9 @@ module axi_adapter #(
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

input logic clk_i,
input logic rst_ni,
input logic clear_i,
output logic busy_o,
input logic req_i,
input ariane_pkg::ad_req_t type_i,
Expand Down Expand Up @@ -461,28 +463,14 @@ module axi_adapter #(
// ----------------
// Registers
// ----------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
// start in flushing state and initialize the memory
state_q <= IDLE;
cnt_q <= '0;
cache_line_q <= '0;
addr_offset_q <= '0;
id_q <= '0;
amo_q <= ariane_pkg::AMO_NONE;
size_q <= '0;
outstanding_aw_cnt_q <= '0;
end else begin
state_q <= state_d;
cnt_q <= cnt_d;
cache_line_q <= cache_line_d;
addr_offset_q <= addr_offset_d;
id_q <= id_d;
amo_q <= amo_d;
size_q <= size_d;
outstanding_aw_cnt_q <= outstanding_aw_cnt_d;
end
end
`FFARNC(state_q, state_d, clear_i, IDLE, clk_i, rst_ni)
`FFARNC(cnt_q, cnt_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(cache_line_q, cache_line_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(addr_offset_q, addr_offset_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(id_q, id_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(amo_q, amo_d, clear_i, ariane_pkg::AMO_NONE, clk_i, rst_ni)
`FFARNC(size_q, size_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(outstanding_aw_cnt_q, outstanding_aw_cnt_d, clear_i, '0, clk_i, rst_ni)

function automatic axi_pkg::atop_t atop_from_amo(ariane_pkg::amo_t amo);
axi_pkg::atop_t result = 6'b000000;
Expand Down
16 changes: 5 additions & 11 deletions core/cache_subsystem/cache_ctrl.sv
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Expand Up @@ -17,6 +17,7 @@
//
// Description: Cache controller

`include "common_cells/registers.svh"

module cache_ctrl
import ariane_pkg::*;
Expand All @@ -26,6 +27,7 @@ module cache_ctrl
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic clear_i, // Synchronous clear active high
input logic bypass_i, // enable cache
output logic busy_o,
input logic stall_i, // stall new memory requests
Expand Down Expand Up @@ -442,17 +444,9 @@ module cache_ctrl
// --------------
// Registers
// --------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
state_q <= IDLE;
mem_req_q <= '0;
hit_way_q <= '0;
end else begin
state_q <= state_d;
mem_req_q <= mem_req_d;
hit_way_q <= hit_way_d;
end
end
`FFARNC(state_q, state_d, clear_i, IDLE, clk_i, rst_ni)
`FFARNC(mem_req_q, mem_req_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(hit_way_q, hit_way_d, clear_i, '0, clk_i, rst_ni)

//pragma translate_off
`ifndef VERILATOR
Expand Down
17 changes: 9 additions & 8 deletions core/cache_subsystem/cva6_hpdcache_if_adapter.sv
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Expand Up @@ -9,6 +9,9 @@
// Authors: Cesar Fuguet
// Date: February, 2023
// Description: Interface adapter for the CVA6 core

`include "common_cells/registers.svh"

module cva6_hpdcache_if_adapter
import hpdcache_pkg::*;

Expand All @@ -26,6 +29,7 @@ module cva6_hpdcache_if_adapter
// Clock and active-low reset pins
input logic clk_i,
input logic rst_ni,
input logic clear_i,

// Port ID
input hpdcache_pkg::hpdcache_req_sid_t hpdcache_req_sid_i,
Expand Down Expand Up @@ -108,7 +112,7 @@ module cva6_hpdcache_if_adapter
logic [ 7:0] amo_data_be;
hpdcache_req_op_t amo_op;
logic [31:0] amo_resp_word;
logic amo_pending_q;
logic amo_pending_q, amo_pending_n;

// AMO logic
// {{{
Expand Down Expand Up @@ -195,16 +199,13 @@ module cva6_hpdcache_if_adapter
: hpdcache_rsp_i.rdata[0];
// }}}

always_ff @(posedge clk_i or negedge rst_ni) begin : amo_pending_ff
if (!rst_ni) begin
amo_pending_q <= 1'b0;
end else begin
amo_pending_q <=
assign amo_pending_n =
( cva6_amo_req_i.req & hpdcache_req_ready_i & ~amo_pending_q) |
(~cva6_amo_resp_o.ack & amo_pending_q);
end
end

`FFARNC(amo_pending_q, amo_pending_n, clear_i, 1'b0, clk_i, rst_ni)
end

// }}}
endgenerate
// }}}
Expand Down
4 changes: 4 additions & 0 deletions core/cache_subsystem/cva6_hpdcache_subsystem.sv
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Expand Up @@ -109,6 +109,7 @@ module cva6_hpdcache_subsystem
) i_cva6_icache (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (1'b0),
.flush_i (icache_flush_i),
.en_i (icache_en_i),
.miss_o (icache_miss_o),
Expand Down Expand Up @@ -226,6 +227,7 @@ module cva6_hpdcache_subsystem
) i_cva6_hpdcache_load_if_adapter (
.clk_i,
.rst_ni,
.clear_i('0),

.hpdcache_req_sid_i(hpdcache_pkg::hpdcache_req_sid_t'(r)),

Expand All @@ -252,6 +254,7 @@ module cva6_hpdcache_subsystem
) i_cva6_hpdcache_store_if_adapter (
.clk_i,
.rst_ni,
.clear_i('0),

.hpdcache_req_sid_i(hpdcache_pkg::hpdcache_req_sid_t'(NumPorts - 1)),

Expand All @@ -278,6 +281,7 @@ module cva6_hpdcache_subsystem
) i_cva6_hpdcache_cmo_if_adapter (
.clk_i,
.rst_ni,
.clear_i('0),

.dcache_req_sid_i(hpdcache_pkg::hpdcache_req_sid_t'(NumPorts)),

Expand Down
51 changes: 21 additions & 30 deletions core/cache_subsystem/cva6_icache.sv
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Expand Up @@ -24,6 +24,7 @@
// 3) NC accesses to I/O space are expected to return 32bit from memory.
//

`include "common_cells/registers.svh"

module cva6_icache
import ariane_pkg::*;
Expand All @@ -35,6 +36,7 @@ module cva6_icache
) (
input logic clk_i,
input logic rst_ni,
input logic clear_i,

/// flush the icache, flush and kill have to be asserted together
input logic flush_i,
Expand Down Expand Up @@ -494,32 +496,16 @@ module cva6_icache
);
end


always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if (!rst_ni) begin
cl_tag_q <= '0;
flush_cnt_q <= '0;
vaddr_q <= '0;
cmp_en_q <= '0;
cache_en_q <= '0;
flush_q <= '0;
state_q <= FLUSH;
cl_offset_q <= '0;
repl_way_oh_q <= '0;
inv_q <= '0;
end else begin
cl_tag_q <= cl_tag_d;
flush_cnt_q <= flush_cnt_d;
vaddr_q <= vaddr_d;
cmp_en_q <= cmp_en_d;
cache_en_q <= cache_en_d;
flush_q <= flush_d;
state_q <= state_d;
cl_offset_q <= cl_offset_d;
repl_way_oh_q <= repl_way_oh_d;
inv_q <= inv_d;
end
end
`FFARNC(cl_tag_q, cl_tag_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(flush_cnt_q, flush_cnt_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(vaddr_q, vaddr_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(cmp_en_q, cmp_en_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(cache_en_q, cache_en_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(flush_q, flush_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(state_q, state_d, clear_i, FLUSH, clk_i, rst_ni)
`FFARNC(cl_offset_q, cl_offset_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(repl_way_oh_q, repl_way_oh_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(inv_q, inv_d, clear_i, '0, clk_i, rst_ni)

///////////////////////////////////////////////////////
// assertions
Expand Down Expand Up @@ -559,10 +545,15 @@ module cva6_icache
vld_mirror <= '{default: '0};
tag_mirror <= '{default: '0};
end else begin
for (int i = 0; i < ICACHE_SET_ASSOC; i++) begin
if (vld_req[i] & vld_we) begin
vld_mirror[vld_addr][i] <= vld_wdata[i];
tag_mirror[vld_addr][i] <= cl_tag_q;
if (clear_i) begin
vld_mirror <= '{default: '0};
tag_mirror <= '{default: '0};
end else begin
for (int i = 0; i < ICACHE_SET_ASSOC; i++) begin
if (vld_req[i] & vld_we) begin
vld_mirror[vld_addr][i] <= vld_wdata[i];
tag_mirror[vld_addr][i] <= cl_tag_q;
end
end
end
end
Expand Down
22 changes: 9 additions & 13 deletions core/cache_subsystem/cva6_icache_axi_wrapper.sv
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Expand Up @@ -13,6 +13,8 @@
// Description: wrapper module to connect the L1I$ to a 64bit AXI bus.
//

`include "common_cells/registers.svh"

module cva6_icache_axi_wrapper
import ariane_pkg::*;
import wt_cache_pkg::*;
Expand All @@ -23,6 +25,7 @@ module cva6_icache_axi_wrapper
) (
input logic clk_i,
input logic rst_ni,
input logic clear_i,
input riscv::priv_lvl_t priv_lvl_i,

input logic flush_i, // flush the icache, flush and kill have to be asserted together
Expand Down Expand Up @@ -109,6 +112,7 @@ module cva6_icache_axi_wrapper
) i_cva6_icache (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (clear_i),
.flush_i (flush_i),
.en_i (en_i),
.miss_o (miss_o),
Expand Down Expand Up @@ -137,6 +141,7 @@ module cva6_icache_axi_wrapper
) i_axi_shim (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (clear_i),
.rd_req_i (axi_rd_req),
.rd_gnt_o (axi_rd_gnt),
.rd_addr_i (axi_rd_addr),
Expand Down Expand Up @@ -191,18 +196,9 @@ module cva6_icache_axi_wrapper
end

// Registers
always_ff @(posedge clk_i or negedge rst_ni) begin : p_rd_buf
if (!rst_ni) begin
req_valid_q <= 1'b0;
req_data_q <= '0;
first_q <= 1'b1;
rd_shift_q <= '0;
end else begin
req_valid_q <= req_valid_d;
req_data_q <= req_data_d;
first_q <= first_d;
rd_shift_q <= rd_shift_d;
end
end
`FFARNC(req_valid_q, req_valid_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(req_data_q, req_data_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(first_q, first_d, clear_i, 1'b1, clk_i, rst_ni)
`FFARNC(rd_shift_q, rd_shift_d, clear_i, '0, clk_i, rst_ni)

endmodule // cva6_icache_axi_wrapper
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