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Halt-on-reset (resethaltreq) not implemented — hasresethaltreq hardwired 0, no dm_top port

enhancementNew feature or requestNew feature or request

Status: Open.

#187 In pulp-platform/riscv-dbg;

· siju-felsite opened on Jun 28, 2026

Debug memory: 16kB vs 4kB

Status: Open.

#179 In pulp-platform/riscv-dbg;

· suppamax opened on Jan 23, 2025

dmi_bscane_tap synthesis problem in Vivado 2023.2

Status: Open.

#178 In pulp-platform/riscv-dbg;

· andreondra opened on Jan 8, 2025

Behaviour when JTAG clock is much faster than the system clock

Status: Open.

#163 In pulp-platform/riscv-dbg;

· rswarbrick opened on May 29, 2024

dmcontrol.haltreq should always read as 0

Status: Open.

#161 In pulp-platform/riscv-dbg;

· bcstrongx opened on May 21, 2024

[sba] Add support for response timeout

Status: Open.

#128 In pulp-platform/riscv-dbg;

· sriyerg opened on Mar 17, 2022

Feature request: Update DM according to debug spec V1.0.0

Status: Open.

#119 In pulp-platform/riscv-dbg;

· silabs-oysteink opened on Oct 19, 2021

low power design considerations

Status: Open.

#114 In pulp-platform/riscv-dbg;

· lighteningfingers opened on Jul 3, 2021

BusWidth is used to set data and address width

enhancementNew feature or requestNew feature or request

Status: Open.

#21 In pulp-platform/riscv-dbg;

· zarubaf opened on May 24, 2019