FROMLIST: arm64: dts: qcom: Add PMIC thermal support for Agatti QRB210-RB1 platform - #1745
Open
raryan-qcom wants to merge 24 commits into
Open
FROMLIST: arm64: dts: qcom: Add PMIC thermal support for Agatti QRB210-RB1 platform#1745raryan-qcom wants to merge 24 commits into
raryan-qcom wants to merge 24 commits into
Conversation
…auxiliary driver The SDAM0 IRQ can be triggered for both EOC (end of conversion) events for immediate ADC reads done in this driver and for threshold violation events, based on ADC_TM thresholds configured from the auxiliary ADC_TM driver on TM channels on the first SDAM. At present, this interrupt is handled only in the ISR in the main ADC driver. When the ISR is triggered for an ADC_TM event, this driver notifies the ADC_TM driver by calling a notifier callback exposed from it for this purpose. To simplify the interrupt handling in both drivers, share the interrupt between the drivers. With this, ADC_TM interrupts on SDAM0 will be handled directly in the ADC_TM driver, so remove the notifier callback and all TM interrupt handling in the main ADC ISR. Link: https://lore.kernel.org/all/20260526-gen3_adc_tm-v2-1-702fbac919ac@oss.qualcomm.com/ Reviewed-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
…oring Add support for ADC_TM part of PMIC5 Gen3. This is an auxiliary driver under the Gen3 ADC driver, which implements the threshold setting and interrupt generating functionalities of QCOM ADC_TM drivers, used to support thermal trip points. Link: https://lore.kernel.org/all/20260526-gen3_adc_tm-v2-2-702fbac919ac@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add macro definitions for virtual channels (combination of ADC channel number and PMIC SID number), to be used in devicetree by clients of ADC5 GEN3 device and in the "reg" property of ADC channels. Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-1-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add ADC nodes for the four PMM8654au PMICs (pmm8654au_0 through pmm8654au_3) on the Lemans platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Also add the io-channels and io-channel-names properties under the temp-alarm nodes so that they can get temperature reading from the ADC die_temp channels. Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-2-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add ADC nodes for PMM8620AU PMIC instances (SID 0 and SID 2) present on the Monaco platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Link: https://lore.kernel.org/all/20260430-adc5_gen3_dt-v1-3-ab2bb40fd490@oss.qualcomm.com/ Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add bindings for the Qualcomm MBG (Master Bandgap) temperature alarm peripheral found on the PM8775 PMIC. Unlike the existing SPMI temp alarm peripheral, the MBG peripheral supports both hot and cold thresholdi monitoring across two programmable levels (LVL1 and LVL2), with interrupt status reported via a fault status register over SPMI. Link: https://lore.kernel.org/all/20260601-spmi-mbg-driver-v1-1-b4892b55a17f@oss.qualcomm.com/ Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Co-developed-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com> Signed-off-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com>
Add driver for the Qualcomm MBG thermal monitoring device. It monitors the die temperature, and when there is a level 1 upper threshold violation, it receives an interrupt over spmi. The driver reads the fault status register and notifies thermal accordingly. Link: https://lore.kernel.org/all/20260601-spmi-mbg-driver-v1-2-b4892b55a17f@oss.qualcomm.com/ Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Co-developed-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com> Signed-off-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com>
Add ADC node and define channels for: - Die temperature for PMK8550, PM8550VE* and PMC8380* PMICs. - PM8550: Die temperature, VPH power, and system thermistors. Define thermal zones 'sys-0-thermal' through 'sys-6-thermal' which correspond to the off-PMIC system thermistors connected via PM8550 AMUX/GPIO lines. Also,add io-channels and io-channel-names properties to the temp_alarm nodes so that they can get temperature reading from the ADC die_temp channels. Link: https://lore.kernel.org/all/20260614-adc5_gen3_dt-v2-4-32ec576c5865@oss.qualcomm.com/ Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
…otification handling
When the system is suspended and a UCSI event arrives (such as USB plug-in),
the GLINK interrupt (with IRQF_NO_SUSPEND flag) fires and it eventually calls
the pmic_glink_ucsi_callback(), which schedules notify_work to handle the
connector change. However, since no wakeup source is held, the system can
re-enter suspend soon after the interrupt handler returns, before notify_work
has completed running, and the USB plug-in event would not be handled.
There was an earlier attempt to address this at the GLINK driver level, by
making the GLINK interrupt wakeup-capable, ("rpmsg: glink: Make glink smem
interrupt wakeup capable") [1], but upstream reviewers suggested a
different approach, preferring wakeup logic to be handled in the client driver.
To avoid losing UCSI notifications in this way, register ucsi_glink
as a wakeup-capable device in the probe, and call pm_wakeup_ws_event()
with hard=true before scheduling notify_work. The hard wakeup aborts any
in-progress suspend, and the timed wakeup source keeps the system
awake long enough for the notify_work call to run.
[1] https://lore.kernel.org/all/20240603073648.3475123-1-quic_deesin@quicinc.com/
Link: https://lore.kernel.org/all/20260710-ucsi_glink_wakeup-v1-1-7d97ea628d92@oss.qualcomm.com/
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
…elay-us Add the standard 'regulator-off-on-delay-us' property to the list of allowed properties for RPMh regulators. This property is required for platforms where specific rails (like camera LDOs) rely on passive discharge and need a mandatory off-time constraint enforced by the regulator core. Link: https://lore.kernel.org/all/20260127190211.14312-2-bjsaikiran@gmail.com/ Signed-off-by: Saikiran <bjsaikiran@gmail.com>
…y-us The core regulator framework supports enforcing a physical off-time via standard properties, but the `qcom-rpmh-regulator` driver currently ignores them. The issue is platform-specific: The Lenovo Yoga Slim 7x (Snapdragon X Elite) has large bulk capacitors on the camera rails (LDO1, LDO3, LDO7). When these regulators are disabled, the voltage decays very slowly (passive discharge). If the rail is re-enabled before this discharge completes, the sensor experiences a brownout and fails to initialize. Add support for parsing the 'regulator-off-on-delay-us' property from the device tree to enforce this physical constraint. Link: https://lore.kernel.org/all/20260127190211.14312-3-bjsaikiran@gmail.com/ Signed-off-by: Saikiran <bjsaikiran@gmail.com>
…m5_get_temp Commit bb21ee3 ("iio: Fix iio_multiply_value use in iio_read_channel_processed_scale") fixed the iio_read_channel_processed_scale to return 0 on success instead of IIO_VAL_INT (1). The existing check in adc_tm5_get_temp() treated a successful return as an error because it expected IIO_VAL_INT. Drop the redundant `ret != IIO_VAL_INT` condition and rely solely on the negative error check. Link: https://lore.kernel.org/all/20260724-adc-tm5-drop-iio-val-int-check-v1-1-0b85a0895dd7@oss.qualcomm.com/ Fixes: bb21ee3 ("iio: Fix iio_multiply_value use in iio_read_channel_processed_scale") Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made for improved performance, mostly at the hardware level. The main differences are increased ratiometric conversion resolution (from 14 bits to 16 bits) and increased bit field width for PMIC SID (to allow communication with an increased number of PMICs, supported on latest SoCs). Link: https://lore.kernel.org/all/20260731-pmic5_gen4_adc-v1-1-9c49b2eea6f9@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
…en4 ADC PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made for improved performance, mostly at the hardware level. One significant software change is that ratiometric conversion resolution has been increased from 14 bits to 16 bits, so the maximum value of these measurements needs to be updated for Gen4. Add a new scaling function for thermistor channels which use this type of conversion. In the latest PMIC arbiter version (v8), there can be up to 4 buses under the PMIC arbiter and 32 PMICs under each bus. In order to support communication between ADC on the master PMIC and ADCs on any of the other PMICs, a field of width 2 bits is added for bus index and the bits for SID are extended from 4 to 5 bits, in the SID register. Add support for this. In addition, it is possible that the master PMIC has ADC of one generation and it needs to communicate with another PMIC with ADC of a different generation. Add new DT properties "qcom,adc5-gen3" and "qcom,adc5-gen4", to distinguish Gen3 channels under a Gen4 master and Gen4 channels under a Gen3 master respectively, to ensure that their conversions are handled correctly. Link: https://lore.kernel.org/all/20260731-pmic5_gen4_adc-v1-2-9c49b2eea6f9@oss.qualcomm.com/ Co-developed-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
… PMIC5 Gen4 ADC PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made for improved performance, mostly at the hardware level. One significant software change is that ratiometric conversion resolution has been increased from 14 bits to 16 bits. Add a reverse scaling function for Gen4 ADC thermistor channels. In the latest PMIC arbiter version (v8), there can be up to 4 buses under the PMIC arbiter and 32 PMICs under each bus. In order to support communication between ADC on the master PMIC and ADCs on any of the other PMICs, a field of width 2 bits is added for bus index and the bits for SID are extended from 4 to 5 bits, in the SID register. Add support for this. Link: https://lore.kernel.org/all/20260731-pmic5_gen4_adc-v1-3-9c49b2eea6f9@oss.qualcomm.com/ Co-developed-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add macro definitions for virtual channels (combination of ADC channel number, PMIC SID number and PMIC bus ID number), to be used in devicetree by clients of ADC5 GEN4 device and in the "reg" property of ADC channels. Link: https://lore.kernel.org/all/20260731-pmic5_gen4_adc-v1-4-9c49b2eea6f9@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
PMK8850 has an ADC5 Gen4 peripheral that acts as the master ADC for the platform, communicating with ADC peripherals on other PMICs on the system. Add the ADC peripheral node with PMK8850 die_temp and xo_therm channel nodes under it initially. Link: https://lore.kernel.org/all/20260731-pmic5_gen4_adc-v1-5-9c49b2eea6f9@oss.qualcomm.com/ Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
…ply support Extend the qcom_battmgr driver to report up to MAX_USB_PORTS (3) USB-C power supply ports on the X1E80100 & Glymur platform, which exposes more than one charger port to firmware. At firmware-enable time, query USB_NUM_PORTS over the existing BATTMGR_USB_PROPERTY_GET opcode to discover how many ports the firmware actually reports, and register the additional "qcom-battmgr-usb2"/"qcom-battmgr-usb3" power supplies only when the firmware confirms a second/third port. Each additional port is polled independently via new BATTMGR_USB2_PROPERTY_GET/SET (0xC0/0xC1) and BATTMGR_USB3_PROPERTY_GET/SET (0xC2/0xC3) opcodes so its properties are not aliased to the primary port's state. Also add the POWER_SUPPLY_PROP_CAPACITY entry to x1e80100_bat_props[]. Link: https://lore.kernel.org/all/20260801-b4-battmgr-multiport-usb-v1-1-89d90bf5de1f@oss.qualcomm.com/_ Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
…t properties The pmic_glink driver can now register an RTC auxiliary device on glymur, whose PMIC exposes an RTC over GLINK (see rtc-glink driver). Document the allow-set-time flag it consumes from the parent pmic-glink node. Link: https://lore.kernel.org/all/20260807-rtc-glink-cleanup-v1-1-7801e4d69c4f@oss.qualcomm.com/ Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Raj Aryan <raryan@qti.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
…pmic_glink Add a new RTC driver that communicates with the PMIC firmware over the GLINK transport layer. The driver supports reading time and alarm functionality via GET_PROPERTY and SET_PROPERTY opcodes. Time is read via GET_PROPERTY (opcode 0x62) using QCOM_RTC_GLINK_TIME property (0x00). Alarm set and enable are handled via SET_PROPERTY (opcode 0x63) using QCOM_RTC_GLINK_ALARM and QCOM_RTC_GLINK_ALARM_ENABLE properties respectively. GET_PROPERTY and SET_PROPERTY responses share the same firmware message layout, with the firmware echoing back the property value. Both opcodes are handled by a common callback path accordingly. Also extend pmic_glink to register the RTC as a PMIC GLINK client and add PMIC GLINK RTC client support for glymur. Link: https://lore.kernel.org/all/20260807-rtc-glink-cleanup-v1-2-7801e4d69c4f@oss.qualcomm.com/ Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Raj Aryan <raryan@qti.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
…ower supply support" This reverts commit 640161c. Signed-off-by: Raj Aryan <raryan@qti.qualcomm.com>
…ply support Extend the qcom_battmgr driver to report up to MAX_USB_PORTS (3) USB-C power supply ports on the X1E80100 & Glymur platform, which exposes more than one charger port to firmware. At firmware-enable time, query USB_NUM_PORTS over the existing BATTMGR_USB_PROPERTY_GET opcode to discover how many ports the firmware actually reports, and register the additional "qcom-battmgr-usb2"/"qcom-battmgr-usb3" power supplies only when the firmware confirms a second/third port. Each additional port is polled independently via new BATTMGR_USB2_PROPERTY_GET/SET (0xC0/0xC1) and BATTMGR_USB3_PROPERTY_GET/SET (0xC2/0xC3) opcodes so its properties are not aliased to the primary port's state. X1E80100 ports report their USB-C adapter type on USB_ADAP_TYPE rather than the SM8350/SC8280XP USB_TYPE property, so add a dedicated x1e80100_usb_prop_map[] mapping POWER_SUPPLY_PROP_USB_TYPE to USB_ADAP_TYPE, and use it for all three X1E80100 USB ports. Give the primary X1E80100 USB port its own update/get_property callback (qcom_battmgr_usb_x1e80100_update()/ qcom_battmgr_usb_x1e80100_get_property()) instead of routing it through the SC8280XP battery-status update path, mirroring the pattern already used for the usb2/usb3 ports. Also add the POWER_SUPPLY_PROP_CAPACITY entry to x1e80100_bat_props[]. Link: https://lore.kernel.org/all/20260806-b4-battmgr-multiport-usb-v2-1-1a6dd1e06cc2@oss.qualcomm.com/ Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
This is a patch which enables ADC and RTC_GLINK defconfigs probe for temp-alarm and rtc-glink depend on these defconfigs. Signed-off-by: Raj Aryan <raryan@qti.qualcomm.com>
…10-RB1 platform Add ADC channels for msm, quiet and xo thermistors along with their ADC thermal bridge nodes and thermal zones for PMIC thermal mitigation. Link: https://lore.kernel.org/all/20260824-pm4125-adc-thermal-v1-1-3b67ef2eccb2@oss.qualcomm.com/ Signed-off-by: Raj Aryan <raj.aryan@oss.qualcomm.com>
qcomlnxci
requested review from
a team,
QUIC-kamalw,
fenglinw-qcom and
kotarake
and removed request for
a team
August 25, 2026 05:08
jprakash-qc
force-pushed
the
tech/pmic/misc
branch
from
September 1, 2026 08:48
e279b1a to
e7bb366
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
6 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Add ADC channels for msm, quiet and xo thermistors along with their ADC thermal bridge nodes and thermal zones for PMIC thermal mitigation.
Link: https://lore.kernel.org/all/20260824-pm4125-adc-thermal-v1-1-3b67ef2eccb2@oss.qualcomm.com/
CRs-Fixed: 4537660