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Diag log #46
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Diag log #46
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007e86a
plat-qcom: bruin: shikra: add platform support
pawarai123 1a492f0
plat-qcom: wildcat: nord: enable diagnostic ring buffer
pawarai123 dc24310
plat-qcom: wildcat: cacao: enable diagnostic ring buffer
pawarai123 4f0ce7d
plat-qcom: bruin: shikra: enable diagnostic ring buffer
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,17 @@ | ||
| /* SPDX-License-Identifier: BSD-2-Clause */ | ||
| /* | ||
| * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. | ||
| */ | ||
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| #ifndef ARCH_CONFIG_H | ||
| #define ARCH_CONFIG_H | ||
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| #define GICD_BASE UL(0x0f200000) | ||
| #define GICR_BASE UL(0x0f260000) | ||
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| #define IMEM_DIAG_OFFSET UL(0x720) | ||
| #define DIAG_SIZE UL(0x3000) | ||
| #define DIAG_BASE (IMEM_BASE + IMEM_SIZE - DIAG_SIZE) | ||
| #define DIAG_LOG_START_INFO (IMEM_BASE + IMEM_DIAG_OFFSET) | ||
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| #endif /* ARCH_CONFIG_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,11 @@ | ||
| # BRUIN architecture configuration | ||
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| include core/arch/arm/cpu/cortex-armv8-0.mk | ||
| $(call force,CFG_TEE_CORE_NB_CORE,4) | ||
| $(call force,CFG_ARM_GICV3,y) | ||
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| CFG_TZDRAM_START ?= 0xa1400000 | ||
| CFG_TEE_RAM_VA_SIZE ?= 0x400000 | ||
| CFG_TA_RAM_VA_SIZE ?= 0x2100000 | ||
| CFG_TZDRAM_SIZE ?= (CFG_TEE_RAM_VA_SIZE + CFG_TA_RAM_VA_SIZE) | ||
| CFG_NUM_THREADS ?= 4 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,9 @@ | ||
| CFG_DRIVERS_CLK ?= n | ||
| CFG_DRIVERS_QCOM_CLK ?= n | ||
| CFG_QCOM_QFPROM_FUSEPROV ?= n | ||
| CFG_QCOM_QFPROM ?= n | ||
| CFG_QCOM_CMD_DB ?= n | ||
| CFG_QCOM_RPMH_CLIENT ?= n | ||
| CFG_QCOM_PAS_PTA ?= n | ||
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| CFG_QCOM_DIAG_LOG ?= $(CFG_TEE_CORE_DEBUG) | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,17 @@ | ||
| /* SPDX-License-Identifier: BSD-2-Clause */ | ||
| /* | ||
| * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. | ||
| */ | ||
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| #ifndef TARGET_CONFIG_H | ||
| #define TARGET_CONFIG_H | ||
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| #define DRAM0_BASE UL(0x80000000) | ||
| #define DRAM0_SIZE UL(0x80000000) | ||
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| #define GENI_UART_REG_BASE UL(0x04a80000) | ||
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| #define IMEM_BASE UL(0x0c100000) | ||
| #define IMEM_SIZE UL(0x00020000) | ||
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| #endif /* TARGET_CONFIG_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1 @@ | ||
| # Placeholder for Qcom architecture specific makefile |
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Functional bug: enabling diag log on a platform that lacks
TCSR_BOOT_MISC_DETECTbreaks the debug build.This enables
CFG_QCOM_DIAG_LOG(defaulting toCFG_TEE_CORE_DEBUG), which compilesdiag_log.c. That file usesTCSR_BOOT_MISC_DETECTat file scope (inregister_phys_mem_pgdir(...)), but neitherbruin/shikra/target_config.hnorbruin/arch_config.hdefines it (only bobcat/hoya/cacao do). Debug builds for shikra fail to compile. Same issue for nord (wildcat/nord/target.mk, no define inwildcat/arch_config.horwildcat/nord/target_config.h).