FROMGIT: power: supply: qcom_battmgr: fix battery chemistry strncmp … - #81
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FROMGIT: power: supply: qcom_battmgr: fix battery chemistry strncmp …#81tingguoc wants to merge 1340 commits into
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Add a trace event for hardware errors reported by the ARMv8 RAS extension registers. userspace app can monitor this trace event and decode error information. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-17-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit b5a45a89ed06f88be6554ab937a93a5ccea2a2ec)
… messages Two related fixes for processor nodes with ACPI_AEST_PROC_FLAG_SHARED or ACPI_AEST_PROC_FLAG_GLOBAL set (e.g. cluster L3 cache, DSU): 1. aest_dev_is_oncore() returns true for any PROCESSOR_ERROR_NODE, causing shared processor nodes (which use an SPI) to take the cpuhp/PPI path. cpuhp_setup_state() is called instead of aest_online_dev(), so aest_config_irq() is never called and the hardware IRQ-config register is never programmed. Fix aest_dev_is_oncore() to check irq_is_percpu() on the registered IRQ. Only nodes whose FHI or ERI is a per-CPU PPI take the oncore path, nodes with an SPI take aest_online_dev(). 2. alloc_aest_node_name() uses processor_id for the node name of all processor nodes. Shared/global nodes have processor_id=0 (the field is unused when SHARED/GLOBAL is set), so every shared node and the per-PE node for CPU 0 both got the name "processor.0", making error logs ambiguous. For shared/global nodes, build the name as "processor.<resource_type>.<device_id>" (e.g. "processor.cache.1") so each node has a unique, meaningful identifier. Per-PE nodes keep the original "processor.<mpidr>" form. Also add proc_flags to struct aest_event so aest_print() can distinguish shared from per-PE nodes and print an appropriate message. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-1-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 3a8e45a9473d4fe10deb0aed6dcddd5459364d93)
The error counts visible under: /sys/kernel/debug/aest/<dev>/processor<cpu>/<node>/err_count always reported zero, even though corrected errors (CEs) were being serviced by the interrupt handler. aest_oncore_dev_init_debugfs() sets up per CPU debugfs entries but wired them up incorrectly in two places: - this_cpu_ptr(adev->adev_oncore) was used inside for_each_possible_cpu(). This always selects the slot for the CPU executing the init code, so all debugfs files ended up referencing the same per CPU aest_device instance instead of the CPU indicated by the loop variable. - The code referenced adev->nodes[i], i.e. the template nodes allocated before __setup_ppi, rather than the per-CPU copies at percpu_dev->nodes[i]. The IRQ handler updates CE counters in the per-CPU records created by __setup_ppi, the template records are never touched at runtime, so err_count always read as zero. Fix this by: - Using per_cpu_ptr(adev->adev_oncore, cpu) when iterating over CPUs. Wiring debugfs files to percpu_dev->nodes[i] so counters reflect the data updated by the IRQ handler. - Using adev->nodes[i].name for debugfs directory names. The per-CPU node receives name via a shallow memcpy and is not the authoritative source. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-2-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 8e82ad6656396ea34341195d9cc0760864eb9884)
The record_implemented bitmap uses the same semantics as the rest of the driver: a SET bit means the record is NOT implemented (skip it), a CLEAR bit means the record IS implemented (process it). aest_node_init_debugfs() and aest_node_err_count_show() were iterating all record_count records unconditionally, creating debugfs entries and accumulating error counts for unimplemented records too. Fix both functions to skip records where the corresponding bit is set in node->record_implemented, consistent with how aest_node_foreach_record() handles the same bitmap. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-3-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 66ff7ded0f7e818f5b39d4f2b680ec41d2f3c658)
The driver unconditionally calls panic() whenever an unrecoverable, uncontainable UE (UET_UC or UET_UEU) is detected. There is no way for the user to suppress this behaviour, which makes it difficult to test UE injection or to run in environments where a kernel panic on every UE is undesirable. Add a module parameter `aest_panic_on_ue` When set to 0 the driver logs the UE and continues instead of panicking. Usage: # Boot time (kernel cmdline) aest.aest_panic_on_ue=0 # Runtime echo 0 > /sys/module/aest/parameters/aest_panic_on_ue Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-4-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 8c588f197bbc45769b100c1ce9bc739b379774c8)
The Arm Error Source Table (AEST) specification describes how firmware exposes RAS error source topology to the operating system. On ACPI systems this information is provided via the AEST ACPI table. Introduce Device Tree bindings that provide an equivalent description of AEST error sources for DT-based platforms. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-5-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 2f3c8da0cfff461ff2f9cb38fad5db33286b2590)
Add a Device Tree frontend for the Arm AEST RAS framework, allowing the existing AEST core driver to be used on DT-only systems. The DT frontend parses the "arm,aest" Device Tree hierarchy and populates the same internal structures as the ACPI-based implementation. It is initialized at the same layer as ACPI and is mutually exclusive with it, ensuring identical behaviour regardless of the firmware interface in use. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-6-d5d6ffacf0a5@oss.qualcomm.com/ Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 6aff3e676829cbb71b8e6a0c9df504a45ff63955)
Add AEST RAS error source nodes for the Monaco SoC. The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Link: https://lore.kernel.org/all/20260505-aest-devicetree-support-v1-8-d5d6ffacf0a5@oss.qualcomm.com/ Co-developed-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> (cherry picked from commit 965645d7f2020b4a265f79d081682ce456e077fc)
Purwa IOT boards support a different thermal junction temperature specification compared to the base Purwa platform due to package level differences. Update the passive trip thresholds to 105°C to align with the higher temperature specification. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260416-purwa_high_tj-v1-1-b538f98d42da@oss.qualcomm.com (cherry picked from commit fd53d0e0a90e65cbc71d202b8cf6efaf893789ed)
Add a device tree overlay to enable EL2 boot support for the Purwa platform with CAMX configuration. CRs-Fixed: 4546991 Signed-off-by: Ignatius Michael Jihan <mignatiu@qti.qualcomm.com> (cherry picked from commit 8d6e4e962e7e504e94b8b1a42240ad191d9867bd)
A repeater is not required for the PHY to function. On systems with multiple PHY instances connected to a multi-port controller, some PHYs may be unconnected. All PHYs must still probe successfully even without attached repeaters, otherwise the controller probe fails. So make it optional. Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> [abel.vesa@oss.qualcomm.com: commit re-worded to reflect actual reason] Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260302-phy-qcom-m31-eusb2-make-repeater-optional-v2-1-dbf714c72056@oss.qualcomm.com/ (cherry picked from commit 984aa89de0ab9645f8e95840cc3b1ce55526c853)
The gcc_eva_ahb_clk and gcc_eva_xo_clk branch clocks should not be registered as standalone GCC branch clocks. Drop these clocks from the GCC clock list and instead add their CBCR registers to the GCC critical clocks list to ensure they remain enabled during early boot. Fixes: efe5043 ("clk: qcom: gcc: Add support for Global Clock Controller") Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-1-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> (cherry picked from commit 18eab67ef55f11476bf0fc218fa86b02e0d4d831)
…r for Glymur SoC Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-2-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> (cherry picked from commit dc215296393bb0634224eb345853a926abd0bcf2)
Add the Enhanced Video Analytics (EVA) clock controller driver for the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs and resets for the EVA subsystem which handles vision processing workloads. Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-3-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> (cherry picked from commit a9bb2c28f8c98d1012d0f05d0ae61199eb95e84e)
Add lcd_bias fixed regulator (3.3V, controlled via pm8150 GPIO4) Enable mdss, mdss_dsi0, mdss_dsi0_phy nodes Add DLC DLC0697 panel node on DSI0 with reset/enable GPIOs, vddio/bias supplies, and TE pin Configure mdss_dsi0_out with 4-lane data path Set pm8150_l11 to 1232mV for DSI VDDA PHY PLL lock Add tlmm pinctrl states for panel reset, reset-suspend, and TE pin. Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com> (cherry picked from commit 872330a93c804b1c2afede355d49f64a29e91f2d)
…need pwrctrl
pci_pwrctrl_is_required() is used to detect whether a device really
needs the PCI pwrctrl support or not. It is currently used in
pci_pwrctrl_create_device(), but not in pci_pwrctrl_power_{on/off}_device()
APIs. This leads to pwrctrl core trying to power on/off the incompatible
devices like USB hub downstream ports defined in DT.
Hence, add this check to prevent pwrctrl core from poking at wrong
devices. For this purpose, move the pci_pwrctrl_is_required() helper
definition to the top.
Link: https://lore.kernel.org/r/20260421104102.12322-1-manivannan.sadhasivam@oss.qualcomm.com
Fixes: b35cf3b ("PCI/pwrctrl: Add APIs to power on/off pwrctrl devices")
Reported-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
(cherry picked from commit acd6cd0e23c6805184faa5b9a2134ff82021806a)
…es for Monaco The PCIe QMP PHYs on Monaco (QCS8300) require stable reference voltage provided by refgen and reference clock provided by qref. The refgen and qref require power supplies. Add a new sa8775p_qmp_phy_vreg_l list with vdda-qref and vdda-refgen supplies, and use it for qcs8300_qmp_gen4x2, sa8775p_qmp_gen4x2 and sa8775p_qmp_gen4x4 PCIe PHY configurations. Workaround will be reverted once the vote qref regulator for PCIe available in upstream. Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> (cherry picked from commit 02d02c13992d3406125e694216e411203dd2f5bb)
…fgen supplies for PCIe PHYs The PCIe QMP PHYs on QCS8300 require stable reference voltage provided by refgen and reference clock provided by qref. Add vdda-qref-supply and vdda-refgen-supply to pcie0_phy and pcie1_phy nodes on the qcs8300-ride board. Workaround will be reverted once the vote qref regulator for PCIe available in upstream. Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> (cherry picked from commit 64fbefde7acc60f01e9caa4eb689bae60390f66d)
…UHS-I mode SD card is detected as SDHS instead of UHS-I because sdhc_2 was configured with vreg_s4a as vqmmc-supply, which cannot switch between 1.8V and 3.3V. Switch vqmmc-supply to vreg_l2a and update its voltage range to 1800000-2960000 uV to enable proper UHS-I signaling. Link: https://lore.kernel.org/all/20260522105020.3588377-1-mchunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com> (cherry picked from commit 195c20d3e5ac3676a4e11ec40e68dd6afcc17eb1)
…en support The Glymur CRD board includes a FocalTech FT3D81 touchscreen connected to I2C bus.FT3D81 driver is compatible to ft112. Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com> (cherry picked from commit 165f40a00de938b8edd0176323ad9ecd26c16460)
Add TLMM pinctrl states for the DLC0697 DSI panel. This includes configuring GPIO3 for the panel reset signal (active and suspend states) and GPIO86 for the tearing effect (TE) signal using the mdp_vsync_p function. Signed-off-by: Shashank Maurya <ssmaurya@qti.qualcomm.com> (cherry picked from commit 7aa3e6667b315fae478317d505b75023a51360b6)
This reverts commit 46f670f2b85181106503ed4d1c597e080c4c3c3e. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com> (cherry picked from commit 572f9d98870c168b59a75961e5a60efece21e0b8)
With the Iris and Venus driver having more or less feature parity for "HFI 6xx" platforms and with Iris gaining support for SC7280, flip the switch. Use Iris by default for SM8250 and SC7280, the platforms which are supported by both drivers, and use Venus only if Iris is not compiled at all. Use IS_ENABLED to strip out the code and data structures which are used by the disabled platforms. Link: https://lore.kernel.org/all/20260327-venus-iris-flip-switch-v5-4-2f4b6c636927@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> [bod: Moved two conditional compats inside of one ifdef for ci] [bod: Changed IS_V6(core) (0) to ((void)(core), 0) for ci] Signed-off-by: Bryan O'Donoghue <bod@kernel.org> (cherry picked from commit 044ed63ad08f75c3e422dbc4da10affcca7dd713)
… dual-station support When P2P support is enabled, wpa_supplicant creates a p2p-device interface by default, which implicitly consumes one vdev. On systems managed by NetworkManager, this interface cannot be reliably disabled, leaving only two usable interfaces for user configurations. Increase num_vdevs to four for QCA6390 hw2.0, WCN6855 hw2.0/hw2.1, QCA2066 hw2.1, and QCA6698AQ hw2.1 to account for the implicit p2p-device and enable common concurrency scenarios such as AP + AP + STA. This change increases interface concurrency in the two-channel scenario by raising the maximum vdev limit, while keeping other combination rules unchanged. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-05266-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.41 Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Tested-on: QCA2066 hw2.1 PCI WLAN.HSP.1.1-03926.13-QCAHSPSWPL_V2_SILICONZ_CE-2.52297.9 Tested-on: QCA6698AQ hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Link: https://lore.kernel.org/linux-wireless/20260525020711.2590815-1-wei.zhang@oss.qualcomm.com/ Signed-off-by: Wei Zhang <wei.zhang@oss.qualcomm.com> (cherry picked from commit f29363bbe07822e03a7b24180b02cea32379f936)
…rror paths ath12k_mac_vdev_create() has three error path issues that leave arvif in an inconsistent state: 1. When ath12k_wmi_vdev_create() fails, the function returns directly without clearing arvif->ar, which was already set before the WMI call. Subsequent code checking arvif->ar to determine vdev readiness will see a non-NULL value despite no vdev existing in firmware. 2. When ath12k_wmi_send_peer_delete_cmd() fails in err_peer_del, the code jumped to err: skipping the DP peer cleanup and vdev rollback, leaving num_created_vdevs, vdev maps and arvif list membership live. 3. When ath12k_wait_for_peer_delete_done() fails, the code jumped to err_vdev_del: skipping the DP peer cleanup. Fix by changing the ath12k_wmi_vdev_create() failure to goto err instead of returning directly, routing both err_peer_del failure paths through err_dp_peer_del: for proper DP peer and vdev rollback, and consolidating the arvif state cleanup at err:. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: 477cabf ("wifi: ath12k: modify link arvif creation and removal for MLO") Link: https://lore.kernel.org/linux-wireless/20260512044906.1735821-1-wei.zhang@oss.qualcomm.com/ Signed-off-by: Wei Zhang <wei.zhang@oss.qualcomm.com> (cherry picked from commit d086d2fa366aaaa98d273d381637252650c7b12a)
…y link _ieee80211_set_active_links() calls _ieee80211_link_use_channel() for each newly-added link and WARN_ON_ONCE()s if it fails. The call uses assign_on_failure=true, which allows mac80211 to continue despite driver failures, but when a mac80211-level channel validation fails (e.g., combinations check, DFS, or no available radio), drv_assign_vif_chanctx() is never reached. Since ath12k_mac_vdev_create() is only called from that path, arvif->is_created remains false and arvif->ar remains NULL for the failed link. The subsequent drv_change_sta_links() call reaches ath12k_mac_op_change_sta_links(), which allocates an arsta and sets ahsta->links_map |= BIT(link_id) for the broken link before checking whether the link is ready. When the vdev was never created, only station_add() is skipped, but the link remains in links_map. Any subsequent operation iterating links_map and dereferencing arvif->ar without a NULL check will crash. Two observed examples are NULL deref in ath12k_mac_ml_station_remove() on disconnect and in ath12k_mac_op_set_key() when wpa_supplicant installs PTK keys. BUG: Unable to handle kernel NULL pointer dereference at 0x00000000 pc : ath12k_mac_station_post_remove+0x40/0xe8 [ath12k] Call trace: ath12k_mac_station_post_remove+0x40/0xe8 [ath12k] ath12k_mac_op_sta_state+0xb60/0x1720 [ath12k] drv_sta_state+0x100/0xbd8 [mac80211] __sta_info_destroy_part2+0x148/0x178 [mac80211] ieee80211_set_disassoc+0x500/0x678 [mac80211] BUG: Unable to handle kernel NULL pointer dereference at 0x00000000 pc : ath12k_mac_op_set_key+0x1f8/0x2c0 [ath12k] Call trace: ath12k_mac_op_set_key+0x1f8/0x2c0 [ath12k] drv_set_key+0x70/0x100 [mac80211] ieee80211_key_enable_hw_accel+0x78/0x260 [mac80211] ieee80211_add_key+0x16c/0x2ac [mac80211] nl80211_new_key+0x138/0x280 [cfg80211] Fix this by checking arvif->is_created before calling ath12k_mac_alloc_assign_link_sta(). This prevents the broken link from entering links_map, so all subsequent operations iterating the bitmap are protected. The reliability of arvif->is_created across all error paths is ensured by the preceding patch. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Fixes: a27fa61 ("wifi: ath12k: support change_sta_links() mac80211 op") Link: https://lore.kernel.org/linux-wireless/20260512044906.1735821-1-wei.zhang@oss.qualcomm.com/ Signed-off-by: Wei Zhang <wei.zhang@oss.qualcomm.com> (cherry picked from commit f542adb59d7428ee3f278ca80aca382904a30fbb)
Add wcn3988-pmu node with supply regulators and bt-enable-gpios to shikra EVK board DTS files. Update the BT node supply references to use PMU-managed LDOs (vreg_pmu_io/xo/rf/ch0) instead of direct PMIC regulators, and move BT node to the board-specific shikra-evk.dtsi. Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com> (cherry picked from commit 1e015b8fba8f3260b6f8328ec74ae06cf5b47530)
Add gpio-reserved-ranges property to the tlmm node for all three Shikra EVK variants (CQM, CQS, IQS) to mark GPIOs used by the SoC internally and not available for general use. Signed-off-by: Anurag Pateriya <apateriy@qti.qualcomm.com> (cherry picked from commit f85e592b0c3f5e61ae47eab025b1c93da45ebd05)
Rename bt-enable-gpios to swctrl-gpios, add sw_ctrl_default pinctrl state for gpio88, and add missing vreg_pmu_ch1 (ldo4) regulator to wcn3988-pmu node across cqm-evk, cqs-evk and iqs-evk boards. Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com> (cherry picked from commit a1e5396e06e971b04509da73634d77848c41865e)
LT9611C(EX/UXD) is an I2C-controlled chip that Receiver signal/dual port mipi dsi and output hdmi, differences in hardware features: - LT9611C: supports 1-port mipi dsi to hdmi 1.4 - LT9611EX: supports 2-port mipi dsi to hdmi 1.4 - LT9611UXD: supports 2-port mipi dsi to hdmi 1.4/2.0 Link : https://lore.kernel.org/lkml/20260508134009.4582-3-syyang@lontium.com/ Signed-off-by: Sunyun Yang <syyang@lontium.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Mohit Dsor <mdsor@qti.qualcomm.com> (cherry picked from commit c78dc5acc49eadb967b44accbfa8b37aead3ee61)
dev_pm_opp_set_rate(0) removes the vote specified in required-opps but does not actually park the clock, making it run without the necessary power backing. Drop the explicit calls to it. Fixes: c943b49 ("drm/msm/dp: add displayPort driver support") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742781/ Link: https://lore.kernel.org/r/20260728-topic-dpu_power-v1-2-e7783b859a70@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
…nable If a downstream consumer (e.g. drm_bridge_connector attached by the msm/dp driver) registers its HPD callback after an upstream driver has already reported a HPD event through drm_aux_hpd_bridge_notify(), the notification is dropped because bridge->hpd_cb is still NULL. This can affect any user of drm_aux_hpd_bridge_notify() whose downstream consumer arms HPD only after upstream events have started. The race has been observed on Qualcomm X1E-based laptops during boot, when pmic_glink_altmode reports the initial USB-C DP connection state before the DP driver has finished probing and enabled HPD handling on the bridge. The consumer then never observes the initial connected state and the external display remains dark. Cache the last HPD status reported through drm_aux_hpd_bridge_notify() and replay it when HPD is enabled by the downstream consumer. The replay is deferred to a work item so that the replayed HPD notification is delivered outside drm_bridge_hpd_enable()'s call context. This follows the same pattern as display-connector, which also defers an initial HPD notification from .hpd_enable(), but reuses the cached status since aux-hpd-bridge cannot re-detect sink presence on its own. Fixes: e560518 ("drm/bridge: implement generic DP HPD bridge") Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260803-drm-usbdp-preboot-v1-1-2539b362be00@oss.qualcomm.com/
Enable CONFIG_CORESIGHT_CTCU (built as a module) for the arm64-qcom flavour to support the CoreSight TMC Control Unit. The CTCU driver programs the per-ATID byte counters and manages the trace-ID (ATID) filtering for the TMC-ETR sink. This allows trace data from selected sources to be routed and captured into system DDR, which is required to enable DDR-based CoreSight trace on Qualcomm platforms. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Enable CONFIG_CORESIGHT_STM (built as a module) for the arm64 flavour to support the CoreSight System Trace Macrocell. The STM driver registers an STMipi/STPv2 trace source and exposes a stimulus-port interface (via the stm class) that lets software, both kernel subsystems and user space, emit timestamped software trace messages into the CoreSight trace bus. These messages can then be merged with hardware trace and captured at a CoreSight sink for system-level debugging. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
lpass ports numbers have been added but the afe/apm driver never got updated with new max port value that it uses to store dai specific data. There are more than one places these values are cached and always become out of sync. This will result in array out of bounds and weird driver behaviour. To catch such issues, first add a single place where we can define max port and second add a check in common parsing code which can error out before corrupting the memory with out of bounds array access. This should help both avoid and catch these type of mistakes in future. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260402081118.348071-8-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
This reverts commit 60e114f. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
This reverts commit 0243751. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
This reverts commit 3b7fc44. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
This reverts commit 7ee6efc. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
This reverts commit ed4fe7a. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
Qualcomm SPMI PMIC BCL (Battery Current Limiting) is a safety feature that monitors battery or system voltage and current to alert system for overcurrent or undervoltage conditions. It provides: - Real-time voltage and current monitoring - Configurable thresholds per channel - Hardware interrupts when thresholds are violated Add a DeviceTree binding to describe the BCL on Qualcomm's PMICs. Add sensor type to SPMI device list for BCL device. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-1-febe2805e17b@oss.qualcomm.com
Add driver for Qualcomm SPMI PMIC Battery Current Limiting (BCL) hardware monitor. The driver exposes battery voltage and current monitoring through hwmon interface. The BCL driver provides - Real-time voltage and current readings - Configurable threshold-based alarms - Interrupt-driven notifications when thresholds are exceeded - Automatic threshold management with polling-based recovery - Hardware-specific scaling factors and threshold representations Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-2-febe2805e17b@oss.qualcomm.com
Add Battery Current Limiting (BCL) hardware monitor node for hamoa-pmic. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-4-febe2805e17b@oss.qualcomm.com
Add Battery Current Limiting (BCL) hardware monitor node for pm8550 PMIC. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-7-febe2805e17b@oss.qualcomm.com
Enable Qualcomm BCL driver config. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
Add new dai ids entries for LPASS LPI MI2S and SENARY MI2S audio lines. Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260402081118.348071-7-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
Introduces support for the Senary MI2S audio interface in the Qualcomm q6dsp. Add new AFE port IDs for Senary MI2S RX and TX and include the necessary mappings in the port configuration to allow audio routing over the Senary MI2S interface. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Tested-by: Val Packett <val@packett.cool> # sm7325-motorola-dubai Link: https://patch.msgid.link/20260402081118.348071-10-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
Enable CONFIG_STM_PROTO_OST (built as a module) for the arm64 flavour to support the MIPI SyS-T / OST (Open System Trace) protocol driver for the CoreSight STM. The driver implements the OST protocol encoder on top of the STM stimulus ports, framing software trace messages with OST headers before they are emitted onto the CoreSight trace bus. This lets trace tooling identify and demultiplex the software trace streams captured at a CoreSight sink. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
serial: qcom-geni: add force suspend/resume to system sleep callbacks
config: enable coresight configs
UPSTREAM: ASoC: qcom: Add LPASS LPI MI2S DAI support and validate DAI IDs during DT parsing
…run_dpu BACKPORT: drm/msm/dp: Drop dev_pm_opp_set_rate(0)
hwmon: Add Qualcomm SPMI BCL driver
…eCDPpreboot FROMLIST: drm/bridge: aux-hpd-bridge: replay last HPD status on hpd_e…
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…ength The battery_chemistry field is a 4-byte array without guaranteed null termination. Using BATTMGR_CHEMISTRY_LEN (4) as the strncmp length for 3-character string literals implicitly requires chemistry[3] == '\0', which may not hold. Use 3 instead to match only the significant bytes. Link: https://lore.kernel.org/all/20260812-fix-qcom-batt-chemistry-strn-v1-1-458545e02641@oss.qualcomm.com/ Signed-off-by: Tingguo Cheng <tingguo.cheng@oss.qualcomm.com>
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FROMGIT: power: supply: qcom_battmgr: fix battery chemistry strncmp
The battery_chemistry field is a 4-byte array without guaranteed null termination. Using BATTMGR_CHEMISTRY_LEN (4) as the strncmp length for 3-character string literals implicitly requires chemistry[3] == '\0', which may not hold. Use 3 instead to match only the significant bytes.
Link: https://lore.kernel.org/all/20260812-fix-qcom-batt-chemistry-strn-v1-1-458545e02641@oss.qualcomm.com/
CRs-Fixed: 4562260