4lane support for IMX708 #7057
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4lane support for IMX708 #7057
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Bah, I hate the handling of 64bit division on 32bit kernels. Hopefully resolved now. |
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naushir
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Sep 22, 2025
V4L2_CCI removes the duplication of handling sensor registers that represent 8, 16, 24, 32, or 64 bit values, and is preferred over sensor drivers hard coding register widths. Switch imx708 to use this way of addressing registers. Signed-off-by: Dave Stevenson <[email protected]>
Exposure, analogue gain, and digital gain are all being set from the tables of registers as well as via the control handler. The value in the tables is therefore redundant, so remove them. Signed-off-by: Dave Stevenson <[email protected]>
Rather than the 3 hard coded PLL settings for 447, 450, and 453MHz, compute the PLL settings based on device tree. Signed-off-by: Dave Stevenson <[email protected]>
The line_length_pix value was duplicated between the register tables and the mode descriptor, so remove from the tables and set it programmatically. Signed-off-by: Dave Stevenson <[email protected]>
Currently this is still at the same pixel rates and hence frame rates as over 2 lanes. Signed-off-by: Dave Stevenson <[email protected]>
Removing more duplication between register tables and mode descriptors, compute the pixel rate registers rather than hard coding the PLL multipliers in the register tables. Signed-off-by: Dave Stevenson <[email protected]>
As the driver now supports 4 data lane readout, and it as an option to the overlay Signed-off-by: Dave Stevenson <[email protected]>
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This gets IMX708 working in 4 lane mode.
It hasn't yet changed the frame rates achievable, but has made it easier in computing the PLL register settings based on the configured values.
Whilst we could try to do something clever in automatically computing values, I'd probably lean towards having an array for
line_length_pixandpixel_ratefor each mode, with one set of values for 2 lanes and another for 4 lanes. At least that way we can guarantee that the value combinations work, but does limit some of the gain in increasing the link frequency.I haven't added any validation on the link frequency actually making a usable system. Adding a check later that the line time of the pixel array is greater than that of the MIPI link would probably be beneficial.