Add syntax for SystemVerilog style part selects #1354
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This commits adds syntax to the parser for SystemVerilog-style part select operators, `v[n +: m]` and `v[n -: m]`. Currently these are allowed in both expressions and L-expressions. More work is needed to support these in bitfield definitions. Right now these aren't implemented, so any attempt to use results in ``` REPL:2> v[n -: m] Syntax error: REPL:2.2-8: 2 |v[n -: m] | ^----^ | Reserved vector indexing syntax. | | This syntax is not currently implemented, but is reserved for future syntax extensions. ``` To push further into the language I think the L-expression type needs to be re-factored so backends can handle all these operators in a clean way. This also potentially opens the door to parsing half-open ranges, which is another requested feature - although the exact syntax for that would require more consideration.
Test Results 13 files 28 suites 0s ⏱️ For more details on these errors, see this check. Results for commit 247abe9. |
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This commits adds syntax to the parser for SystemVerilog-style part select operators,
v[n +: m]andv[n -: m]. Currently these are allowed in both expressions and L-expressions. More work is needed to support these in bitfield definitions.Right now these aren't implemented, so any attempt to use results in
To push further into the language I think the L-expression type needs to be re-factored so backends can handle all these operators in a clean way.
This also potentially opens the door to parsing half-open ranges, which is another requested feature - although the exact syntax for that would require more consideration.