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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture

Welcome to the RISC-V Non-ISA Specifications 👋

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Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.7k 256

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 857 183

  3. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 484 99

  4. riscv-rvv-intrinsic-doc riscv-rvv-intrinsic-doc Public

    C 381 112

  5. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 225 57

  6. riscv-iommu riscv-iommu Public

    RISC-V IOMMU Specification

    C 172 35

Repositories

Showing 10 of 36 repositories
  • riscv-rpmi Public

    RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control

    riscv-non-isa/riscv-rpmi's past year of commit activity
    Makefile 25 CC-BY-4.0 17 3 1 Updated Oct 29, 2026
  • riscv-brs Public

    The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

    riscv-non-isa/riscv-brs's past year of commit activity
    Shell 59 CC-BY-4.0 24 17 3 Updated Oct 28, 2026
  • riscv-external-debug-security Public

    The RISC-V External Debug Security Specification

    riscv-non-isa/riscv-external-debug-security's past year of commit activity
    Makefile 20 CC-BY-4.0 6 2 0 Updated Oct 28, 2026
  • riscv-iopmp Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/riscv-iopmp's past year of commit activity
    C 42 CC-BY-4.0 11 5 6 Updated Oct 27, 2026
  • riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    riscv-non-isa/riscv-elf-psabi-doc's past year of commit activity
    Python 857 CC-BY-4.0 183 65 26 Updated Oct 27, 2026
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec's past year of commit activity
    C 225 CC-BY-4.0 57 4 0 Updated Oct 23, 2026
  • riscv-ap-tee-io Public

    This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory as well as MMIO, removing the dependence on para-virtualized I/O.

    riscv-non-isa/riscv-ap-tee-io's past year of commit activity
    Makefile 17 CC-BY-4.0 5 7 0 Updated Oct 21, 2026
  • riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    riscv-non-isa/riscv-asm-manual's past year of commit activity
    Makefile 1,656 CC-BY-4.0 256 11 10 Updated Oct 19, 2026
  • riscv-event-trace Public

    Extension to the RISC-V Trace standards which is user-configurable to trace a hardware-filtered subset of instructions

    riscv-non-isa/riscv-event-trace's past year of commit activity
    Makefile 1 CC-BY-4.0 2 0 2 Updated Oct 16, 2026
  • riscv-non-isa/riscv-rvv-intrinsic-doc's past year of commit activity
    C 381 BSD-3-Clause 112 28 12 Updated Oct 15, 2026

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