RISC-V already supports Execute Only Memory (XOM) in hardware, but there is no current support for it in the psABI.
We (Google) plan to submit a proposal to this effect, but want to raise the issue here, both to further discussion and coordination. Roughly speaking, we think RISC-V support should follow the precedent set by ARM in its support for ELF attributes, so that compilers don't emit things like constant islands, which would break under XOM. Though we believe it is unlikely that compilers are emitting such constant pools for RISC-V, these attributes could still be useful for preventing issues with hand written assembly, and for uniformity across toolchain implementations.
CC: @petrhosek, @frobtech, @jrtc27, @kito-cheng
RISC-V already supports Execute Only Memory (XOM) in hardware, but there is no current support for it in the psABI.
We (Google) plan to submit a proposal to this effect, but want to raise the issue here, both to further discussion and coordination. Roughly speaking, we think RISC-V support should follow the precedent set by ARM in its support for ELF attributes, so that compilers don't emit things like constant islands, which would break under XOM. Though we believe it is unlikely that compilers are emitting such constant pools for RISC-V, these attributes could still be useful for preventing issues with hand written assembly, and for uniformity across toolchain implementations.
CC: @petrhosek, @frobtech, @jrtc27, @kito-cheng