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Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH - #1596

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Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH#1596
dansmathers wants to merge 1 commit into
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@dansmathers dansmathers commented Feb 7, 2024

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Refresh encoding.h to update CSR_MINTSTATUS, CSR_SINTSTATUS, CSR_UINTSTATUS addresses to read-only csr addresses and add CSR_MINTTHRESH, CSR_SINTTHRESH, CSR_UINTTHRESH csrs.

spec: https://github.com/riscv/riscv-fast-interrupt

@dansmathers
Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH
4db0202 
Refresh encoding.h to update CSR_MINTSTATUS, CSR_SINTSTATUS, CSR_UINTSTATUS addresses to read-only csr addresses and add CSR_MINTTHRESH, CSR_SINTTHRESH, CSR_UINTTHRESH csrs.

spec: https://github.com/riscv/riscv-fast-interrupt

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
aswaterman
aswaterman requested changes Feb 7, 2024
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encoding.h is an auto-generated file and so shouldn't be edited manually. See the header:

riscv-isa-sim/riscv/encoding.h

Lines 5 to 8 in d4726e1

/*
* This file is auto-generated by running 'make' in
* https://github.com/riscv/riscv-opcodes (a014979)
*/

Please make this change in riscv-opcodes and, after that PR is merged, regenerate encoding.h and copy it over to here.

@dansmathers

dansmathers commented Feb 8, 2024

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created riscv/riscv-opcodes#226

closing pull until riscv-opcodes PR is merged.

@dansmathers dansmathers closed this Feb 8, 2024
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 8, 2024
@dansmathers
Draft: Add m-mode CLIC interrupt testcases
0653f78 
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 8, 2024
@dansmathers
Draft: Add m-mode CLIC interrupt testcases
11afbf0 
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 9, 2024
@dansmathers
Draft: Add s-mode CLIC interrupt testcases
132fe70 
his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 9, 2024
@dansmathers
Draft: Add s-mode CLIC interrupt testcases
547805c 
This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
dansmathers added a commit to dansmathers/riscv-arch-test that referenced this pull request Feb 9, 2024
@dansmathers
Draft: Add m/s-mode CLIC interrupt testcases
34d0c72 
This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
@dansmathers dansmathers mentioned this pull request Feb 9, 2024
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jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add m-mode CLIC interrupt testcases
c239aef 
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add m-mode CLIC interrupt testcases
09cb8de 
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add s-mode CLIC interrupt testcases
68e9b39 
his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add s-mode CLIC interrupt testcases
35ee9c1 
This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond pushed a commit to dansmathers/riscv-arch-test that referenced this pull request Jun 6, 2024
@dansmathers @jamesbeyond
Draft: Add m/s-mode CLIC interrupt testcases
2e3b80b 
This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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