ZicntrS mismatch between Imperas and Sail because in my current config, mcounteren[3] is writable in Sail but read-only-zero in Imperas. Therefore, reading hpmcounter3 from supervisor/user mode is ok in Sail but traps in Imperas. (Same issue in Whisper). There are problems with the trap handler and reporting, such that ZicntrS makes a misleading report.
See attached gizp with the elfs, objdump, and traces to reproduce the issue.
In ZicntrS Sail ref (build/priv/ZicntrS/ZicntrS-00.sig.trace), read to hpmcounter3 succeeds.
mem[X,0x0000000080000678] -> 0x29F3
mem[X,0x000000008000067A] -> 0xC030
[491] [S]: 0x0000000080000678 (0xC03029F3) csrrs x19, hpmcounter3, x0 ZicntrS_cg_cp_mcounteren_access_s_walking_1_3+84
CSR hpmcounter3 (0xC03) -> 0x0000000000000000
x19 <- 0x0000000000000000
In ZicntrS Imperas (logs/ZicntrS/ZicntrS-00.log), read to hpmcounter3 traps.
Info 487: 'iss/cpu0', 0x0000000080000678(ZicntrS_cg_cp_mcounteren_access_s_walking_1_3+54): Supervisor c03029f3 csrr s3,hpmcounter3
Info mstatus 0000000a00000080 -> 0000000a00000800
Info mcause 0000000000000009 -> 0000000000000002
Info mtval 0000000000000000 -> 00000000c03029f3
Info 488: 'iss/cpu0', 0x0000000080008140(Mtrampoline): Machine 1000006f j 80008240
The log file (more visible in ZicntrS-00.log when Imperas tracing is turned off) says
RVCP-SUMMARY: TEST FAILED - Test File "ZicntrS-00.S"
RVCP: DEBUG INFORMATION FOLLOWS
RVCP: Test Info: "Mismatch in mepc value! Trap was being handled in M-Mode."
RVCP: Instruction: 0x01033483
RVCP: Approximate address (failure may be slightly after this): 0x00000000800085ac
RVCP: Register: x8
RVCP: Bad Value: 0x000000000000023c
RVCP: Expected Value: 0x0000000000000f64
RVCP: Address of instruction that trapped (XEPC): 0x0000000080000678
RVCP: Instruction that trapped: 0xc03029f3
RVCP: END OF DEBUG INFORMATION
This report is misleading in a number of ways.
The instruction, approximate address, register, bad value, expected value don't seem to have anything to do with the mismatch.
The root cause is that the DUT trapped and the REF did not. It would be nice if it were possible to just say so, rather than say the true but less insightful "Mismatch in mepc value!"
Maybe something like:
RVCP: Test Info: "Mismatch in mepc value"
RVCP: Bad Value: 0x0000000080000678
RVCP: Expected Value: 0x....
RVCP: If Bad Value < Expected Value, DUT trapped when reference model did not.
RVCP: If Expected Value < Bad Value, Reference model trapped when DUT did not.
RVCP: END OF DEBUG INFORMATION
zicntr.tar.gz
ZicntrS mismatch between Imperas and Sail because in my current config, mcounteren[3] is writable in Sail but read-only-zero in Imperas. Therefore, reading hpmcounter3 from supervisor/user mode is ok in Sail but traps in Imperas. (Same issue in Whisper). There are problems with the trap handler and reporting, such that ZicntrS makes a misleading report.
See attached gizp with the elfs, objdump, and traces to reproduce the issue.
In ZicntrS Sail ref (build/priv/ZicntrS/ZicntrS-00.sig.trace), read to hpmcounter3 succeeds.
In ZicntrS Imperas (logs/ZicntrS/ZicntrS-00.log), read to hpmcounter3 traps.
The log file (more visible in ZicntrS-00.log when Imperas tracing is turned off) says
This report is misleading in a number of ways.
The instruction, approximate address, register, bad value, expected value don't seem to have anything to do with the mismatch.
The root cause is that the DUT trapped and the REF did not. It would be nice if it were possible to just say so, rather than say the true but less insightful "Mismatch in mepc value!"
Maybe something like:
RVCP: Test Info: "Mismatch in mepc value"
RVCP: Bad Value: 0x0000000080000678
RVCP: Expected Value: 0x....
RVCP: If Bad Value < Expected Value, DUT trapped when reference model did not.
RVCP: If Expected Value < Bad Value, Reference model trapped when DUT did not.
RVCP: END OF DEBUG INFORMATION
zicntr.tar.gz