v0.1.0

Release AstraKernel v0.1.0

Warning

AstraKernel v0.1.0 is an experimental, educational project.
It is not stable, secure, or production-ready, and may contain breaking changes in future versions.
Use only for learning and experimentation.
The authors and contributors assume no responsibility for any issues, data loss, or damages resulting from its use.

This is the first release for AstraKernel from the roadmap toward file creation and saving. This release is the first phase of a series of multiple phases.

Phase A – Foundations ~ Kernel Bring-Up

• Bootstrapping: stack setup, BSS clearing, entry into the kernel main.
• UART I/O: putc/puts, getc/getline, basic shell loop.
• Vector Table: Define vector table for exceptions/interrupts.
• Basic Timer Interrupt: Configure one hardware timer, hook its interrupt to increment a "tick" counter.

What's Changed

• puts optional arguments and documentation by @shade5144 in #2
• Datetime using the Real Time Clock by @shade5144 in #3
• 🔥 Feature: Add docker build options by @grivera64 in #5
• Implemented strcmp() and strlen() by @chrisdedman in #4
• CPU Migration by @chrisdedman in #7
• Vector Table Implementation by @chrisdedman in #9
• Basic Timer Interrupt by @chrisdedman in #10

New Contributors

Special thanks to the contributors of this project:

• @shade5144 made their first contribution in #2
• @grivera64 made their first contribution in #5

Full Changelog: https://github.com/sandbox-science/AstraKernel/commits/v0.1.0