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Support ESP v2+ chip feature to divide BRP by 2 #71

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Support ESP v2+ chip feature to divide BRP by 2 #71

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d6d206b
Support ESP v2+ chip feature to divide BRP by 2
Apr 14, 2021
a3ad2c8
Update ESP32SJA1000.cpp
mister0wl Aug 30, 2021
232562c
fix: prevent REG_IER from being overwritten
tzzee Jun 20, 2022
8e06f8c
Merge pull request #1 from tzzee/mister0wl
mister0wl Jan 10, 2023
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127 changes: 79 additions & 48 deletions src/ESP32SJA1000.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -70,54 +70,85 @@ int ESP32SJA1000Class::begin(long baudRate)
modifyRegister(REG_BTR0, 0xc0, 0x40); // SJW = 1
modifyRegister(REG_BTR1, 0x70, 0x10); // TSEG2 = 1

switch (baudRate) {
case (long)1000E3:
modifyRegister(REG_BTR1, 0x0f, 0x04);
modifyRegister(REG_BTR0, 0x3f, 4);
break;

case (long)500E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 4);
break;

case (long)250E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 9);
break;

case (long)200E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 12);
break;

case (long)125E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 19);
break;

case (long)100E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 24);
break;

case (long)80E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 30);
break;

case (long)50E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 49);
break;

/*
Due to limitations in ESP32 hardware and/or RTOS software, baudrate can't be lower than 50kbps.
See https://esp32.com/viewtopic.php?t=2142
*/
default:
return 0;
break;
esp_chip_info_t chip;
esp_chip_info(&chip);

if (baudRate >= 50E3) {

if (chip.revision >= 2) {
modifyRegister(REG_IER, 0x10, 0); // From rev2 used as "divide BRP by 2"
}

switch (baudRate) {
case (long)1000E3:
modifyRegister(REG_BTR1, 0x0f, 0x04);
modifyRegister(REG_BTR0, 0x3f, 4);
break;

case (long)500E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 4);
break;

case (long)250E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 9);
break;

case (long)200E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 12);
break;

case (long)125E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 19);
break;

case (long)100E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 24);
break;

case (long)80E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 30);
break;

case (long)50E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 49);
break;

default:
return 0;
break;
}
}else {

if (chip.revision >= 2) {
modifyRegister(REG_IER, 0x10, 1); // From rev2 used as "divide BRP by 2"
}else {
return 0;
}

switch (baudRate) {

case (long)40E3:
modifyRegister(REG_BTR1, 0x0f, 0x0c);
modifyRegister(REG_BTR0, 0x3f, 30);
break;

case (long)20E3:
modifyRegister(REG_BTR1, 0x0f, 0x4d);
modifyRegister(REG_BTR0, 0x3f, 30);
break;

default:
return 0;
break;
}

}

modifyRegister(REG_BTR1, 0x80, 0x80); // SAM = 1
Expand Down