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DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
Python 114 35
Linear algebra accelerators for RISC-V (published in ICCD 17)
66 8
EDA physical synthesis optimization kit
Verilog 60 11
An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
Verilog 31 14
The Verilog source code for DRUM approximate multiplier.
Verilog 31 11
The official implementation for MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning (CVPR '24)
Python 62 7
AdaMTL: Adaptive Input-dependent Inference for Efficient Multi-Task Learning
markdown code for SCALE website
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Natural Language Exploration of Hardware Designs and Libraries
Android application for AR benchmarking using MTL models.
Official codebase for PoliTune: Analyzing the Impact of Data Selection and Fine-Tuning on Economic and Political Biases in Large Language Models
A Benchmark for Verilog Code Metric Reasoning (ASPDAC'25)
Multi-Task learning model based on SWIN Transformer
Image Restoration Framework
Solving MaxSAT using PyTorch
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