Merge pull request #18 from simoninns/jessica-rabbit

Jessica rabbit

DE0-NANO/DomesdayDuplicator/DomesdayDuplicator.done

@@ -1 +1 @@
-Sat Apr 21 15:11:09 2018
+Sat Jun  2 21:46:49 2018

DE0-NANO/DomesdayDuplicator/DomesdayDuplicator.fit.summary

@@ -1,16 +1,16 @@
-Fitter Status : Successful - Sat Apr 21 15:11:05 2018
+Fitter Status : Successful - Sat Jun  2 21:46:43 2018
 Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition
 Revision Name : DomesdayDuplicator
 Top-level Entity Name : DomesdayDuplicator
 Family : Cyclone IV E
 Device : EP4CE22F17C6
 Timing Models : Final
-Total logic elements : 309 / 22,320 ( 1 % )
-    Total combinational functions : 223 / 22,320 ( < 1 % )
-    Dedicated logic registers : 230 / 22,320 ( 1 % )
-Total registers : 230
+Total logic elements : 296 / 22,320 ( 1 % )
+    Total combinational functions : 272 / 22,320 ( 1 % )
+    Dedicated logic registers : 176 / 22,320 ( < 1 % )
+Total registers : 176
 Total pins : 73 / 154 ( 47 % )
 Total virtual pins : 0
 Total memory bits : 327,680 / 608,256 ( 54 % )
 Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
-Total PLLs : 3 / 4 ( 75 % )
+Total PLLs : 1 / 4 ( 25 % )

DE0-NANO/DomesdayDuplicator/DomesdayDuplicator.map.summary

@@ -1,14 +1,14 @@
-Analysis & Synthesis Status : Successful - Sat Apr 21 15:10:51 2018
+Analysis & Synthesis Status : Successful - Sat Jun  2 21:46:34 2018
 Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition
 Revision Name : DomesdayDuplicator
 Top-level Entity Name : DomesdayDuplicator
 Family : Cyclone IV E
-Total logic elements : 337
-    Total combinational functions : 223
-    Dedicated logic registers : 230
-Total registers : 230
+Total logic elements : 338
+    Total combinational functions : 272
+    Dedicated logic registers : 176
+Total registers : 176
 Total pins : 73
 Total virtual pins : 0
 Total memory bits : 327,680
 Embedded Multiplier 9-bit elements : 0
-Total PLLs : 3
+Total PLLs : 1

DE0-NANO/DomesdayDuplicator/DomesdayDuplicator.qsf

@@ -189,6 +189,4 @@ set_global_assignment -name VERILOG_FILE dataGenerator.v
 set_global_assignment -name VERILOG_FILE fx3StateMachine.v
 set_global_assignment -name VERILOG_FILE convertTenToSixteenBits.v
 set_global_assignment -name QIP_FILE IPfifo.qip
-set_global_assignment -name QIP_FILE ntscPll.qip
-set_global_assignment -name QIP_FILE palPll.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

DE0-NANO/DomesdayDuplicator/DomesdayDuplicator.sta.summary

@@ -2,124 +2,88 @@
 TimeQuest Timing Analyzer Summary
 ------------------------------------------------------------
 
-Type  : Slow 1200mV 85C Model Setup 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -9.618
-TNS   : -1767.119
-
-Type  : Slow 1200mV 85C Model Setup 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -6.077
-TNS   : -1027.050
+Type  : Slow 1200mV 85C Model Setup 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 4.606
+TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Setup 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 6.264
+Slack : 4.712
 TNS   : 0.000
 
-Type  : Slow 1200mV 85C Model Hold 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -1.995
-TNS   : -31.920
-
-Type  : Slow 1200mV 85C Model Hold 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.348
+Type  : Slow 1200mV 85C Model Hold 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.236
 TNS   : 0.000
 
-Type  : Slow 1200mV 85C Model Hold 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.356
+Type  : Slow 1200mV 85C Model Hold 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.358
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 5.997
+Slack : 8.079
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 9.739
+Slack : 9.747
 TNS   : 0.000
 
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 13.841
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 12.244
 TNS   : 0.000
 
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 17.209
+Type  : Slow 1200mV 0C Model Setup 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 5.009
 TNS   : 0.000
 
-Type  : Slow 1200mV 0C Model Setup 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -8.748
-TNS   : -1610.675
-
-Type  : Slow 1200mV 0C Model Setup 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -5.360
-TNS   : -902.583
-
 Type  : Slow 1200mV 0C Model Setup 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 6.856
+Slack : 5.066
 TNS   : 0.000
 
-Type  : Slow 1200mV 0C Model Hold 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -1.911
-TNS   : -30.566
-
-Type  : Slow 1200mV 0C Model Hold 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.311
+Type  : Slow 1200mV 0C Model Hold 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.236
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
 Slack : 0.312
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 5.993
+Slack : 8.076
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 9.708
+Slack : 9.709
 TNS   : 0.000
 
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 13.801
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 12.243
 TNS   : 0.000
 
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 17.196
+Type  : Fast 1200mV 0C Model Setup 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 6.161
 TNS   : 0.000
 
-Type  : Fast 1200mV 0C Model Setup 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -6.313
-TNS   : -1167.508
-
-Type  : Fast 1200mV 0C Model Setup 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -3.242
-TNS   : -525.669
-
 Type  : Fast 1200mV 0C Model Setup 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 8.745
+Slack : 6.228
 TNS   : 0.000
 
-Type  : Fast 1200mV 0C Model Hold 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -1.754
-TNS   : -28.051
-
-Type  : Fast 1200mV 0C Model Hold 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.180
+Type  : Fast 1200mV 0C Model Hold 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.109
 TNS   : 0.000
 
-Type  : Fast 1200mV 0C Model Hold 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.184
+Type  : Fast 1200mV 0C Model Hold 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.186
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 6.002
+Slack : 8.086
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
 Slack : 9.416
 TNS   : 0.000
 
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'palPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 13.788
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'ntscPll0|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 17.137
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'IPpllGenerator0|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 12.251
 TNS   : 0.000
 
 ------------------------------------------------------------

DE0-NANO/DomesdayDuplicator/DomesdayDuplicator.v

@@ -109,7 +109,7 @@ assign fx3_control[10] = GPIO1[07];	// FX3 CTL_10 GPIO_27
 // input3				GPIO_29		CTL_12	Output	- Unused
 
 // outputE0				GPIO_22		CTL_05	Input		- FX3 Configuration bit 0 (Test mode off/on)
-// outputD0				GPIO_23		CTL_06	Input		- FX3 Configuration bit 1 (NTSC sampling/PAL sampling)
+// outputD0				GPIO_23		CTL_06	Input		- FX3 Configuration bit 1 (Unused)
 // outputD1				GPIO_24		CTL_07	Input		- FX3 Configuration bit 2 (DC offset compensation off/on)
 // outputD2				GPIO_25		CTL_08	Input		- FX3 Configuration bit 3 (Unused)
 // outputD3				GPIO_26		CTL_09	Input		- FX3 Configuration bit 4 (Unused)
@@ -119,15 +119,18 @@ wire fx3_nReset;
 wire fx3_dataAvailable;
 wire fx3_collectData;
 wire fx3_readData;
-wire fx3_testMode;
 wire fx3_bufferError;
+wire fx3_testMode;
+wire fx3_dcOffsetMode;
 
 // Signal outputs to FX3
 assign fx3_control[00] 		= fx3_dataAvailable;
 assign fx3_control[03] 		= fx3_bufferError;
-//assign fx3_control[04]	= fx3_unusedInput1;
-//assign fx3_control[11]	= fx3_unusedInput2;
-//assign fx3_control[12]	= fx3_unusedInput3;
+
+// These are currently unused, but must have a defined value
+assign fx3_control[04]	= 0;
+assign fx3_control[11]	= 0;
+assign fx3_control[12]	= 0;
 
 // Signal inputs from FX3
 assign fx3_nReset      = fx3_control[10];
@@ -136,7 +139,7 @@ assign fx3_readData    = fx3_control[01];
 
 // Signal inputs from FX3 (configuration bits)
 assign fx3_testMode    		= fx3_control[05];
-assign fx3_samplingMode    = fx3_control[06];
+//assign fx3_configBit1    = fx3_control[06];
 assign fx3_dcOffsetMode 	= fx3_control[07];
 //assign fx3_configBit3		= fx3_control[07];
 //assign fx3_configBit4 	= fx3_control[07];
@@ -162,7 +165,8 @@ assign adcData[9] = GPIO0[23];
 
 // ADC clock output
 // Select the correct sampling clock based on the configuration
-assign GPIO0[33] = (fx3_samplingMode) ? PalAdc_clock : NtscAdc_clock;
+wire adc_clock;
+assign GPIO0[33] = adc_clock;
 
 // ADC Hardware mapping ends --------------------------------------------------
 
@@ -172,31 +176,14 @@ assign GPIO0[33] = (fx3_samplingMode) ? PalAdc_clock : NtscAdc_clock;
 
 // PLL Functions (clock generation) --------------------------------------------
 
-// Generate 80 MHz FX3/FPGA system clock from the 50 MHz physical clock
+// Generate 60 MHz FX3/FPGA system clock from the 50 MHz physical clock
 IPpllGenerator IPpllGenerator0 (
 	// Inputs
 	.inclk0(CLOCK_50),
 
 	// Outputs
-	.c0(fx3_clock)		// 80 MHz system clock
-);
-
-// Generate 28.63632 MHz NTSC sampling clock from the 50 MHz physical clock
-ntscPll ntscPll0 (
-	// Inputs
-	.inclk0(CLOCK_50),
-
-	// Outputs
-	.c0(NtscAdc_clock)		// 28.63632 MHz NTSC sampling clock (actual 28.636364 MHz)
-);
-
-// Generate 35.46895 MHz PAL sampling clock from the 50 MHz physical clock
-palPll palPll0 (
-	// Inputs
-	.inclk0(CLOCK_50),
-
-	// Outputs
-	.c0(PalAdc_clock)		// 35.46895 MHz PAL sampling clock (actual 35.470085 MHz)
+	.c0(fx3_clock),	// 60 MHz system clock
+	.c1(adc_clock)		// 40 MHz ADC clock
 );
 
 wire fx3isReading;
@@ -205,13 +192,11 @@ wire fx3isReading;
 dataGenerator dataGenerator0 (
 	// Inputs
 	.nReset(fx3_nReset),						// Not reset
-	.NtscAdcClk(NtscAdc_clock),			// Data collection clock (NTSC ADC)
-	.PalAdcClk(PalAdc_clock),				// Data collection clock (PAL ADC)
-	.fx3Clk(fx3_clock),						// Data output clock (FX3)
+	.adc_clock(adc_clock),					// ADC clock
+	.fx3_clock(fx3_clock),					// FX3 clock
 	.collectData(fx3_collectData),		// Collect data (ADC data is discarded if 0)
 	.readData(fx3isReading),				// 1 = FX3 is reading data
 	.testMode(fx3_testMode),				// 1 = Test mode on
-	.samplingMode(fx3_samplingMode),		// 1 = PAL, 0 = NTSC
 	.dcOffsetComp(fx3_dcOffsetMode),		// 1 = compensation on, 0 = compensation off
 	.adcData(adcData),						// ADC data bus input
 
@@ -225,7 +210,7 @@ dataGenerator dataGenerator0 (
 fx3StateMachine fx3StateMachine0 (
 	// Inputs
 	.nReset(fx3_nReset),						// Not reset
-	.inclk(fx3_clock),						// Input clock
+	.fx3_clock(fx3_clock),					// FX3 clock
 	.readData(fx3_readData),				// FX3 is about to start sampling the databus
 
 	// Output

DE0-NANO/DomesdayDuplicator/IPfifo.v

@@ -90,10 +90,10 @@ module IPfifo (
 		dcfifo_component.lpm_width = 10,
 		dcfifo_component.lpm_widthu = 16,
 		dcfifo_component.overflow_checking = "ON",
-		dcfifo_component.rdsync_delaypipe = 4,
+		dcfifo_component.rdsync_delaypipe = 3,
 		dcfifo_component.underflow_checking = "ON",
 		dcfifo_component.use_eab = "ON",
-		dcfifo_component.wrsync_delaypipe = 4;
+		dcfifo_component.wrsync_delaypipe = 3;
 
 
 endmodule
@@ -115,7 +115,7 @@ endmodule
 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
@@ -142,10 +142,10 @@ endmodule
 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "16"
 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
 // Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
 // Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
 // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"

DE0-NANO/DomesdayDuplicator/IPfifo_bb.v

@@ -71,7 +71,7 @@ endmodule
 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
@@ -98,10 +98,10 @@ endmodule
 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "16"
 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
 // Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
 // Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
 // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"

DE0-NANO/DomesdayDuplicator/IPpllGenerator.ppf

@@ -4,6 +4,7 @@
 <global>
 <pin name="inclk0" direction="input" scope="external" source="clock"  />
 <pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
 
 </global>
 </pinplan>