Popular repositories Loading

1. Verilog-Design-Examples Verilog-Design-Examples Public

   Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

   Verilog 93 16

2. 100DaysofRTL 100DaysofRTL Public

   100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edg…

   SystemVerilog 27 3

3. LIN-protocol LIN-protocol Public

   LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

   SystemVerilog 5 1

4. 7T_SRAM 7T_SRAM Public

   7T SRAM Design submitted as a final report for Cloud Based Analog IC Design Hackathon conducted by IITH, Synopsis and VSD

5. snbk001 snbk001 Public

   Config files for my GitHub profile.