Issues · steveicarus/iverilog · GitHub

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Add the Icarus Verilog logo to the documentation

#1356

· hwhsu1231 opened

on May 13, 2026

iverilog `-tvvp` generates non-relocatable absolute VPI module paths

#1344

· rhabacker opened

on May 8, 2026

`always @(negedge)` not triggered on time-0 transition when `initial` is declared first

#1326

· m2kar opened

on Apr 22, 2026

Partially-Driven `output logic` Vector Initializes Undriven Bits to `z` Instead of `x`

#1325

· m2kar opened

on Apr 20, 2026

No warning on dynamic Out-Of-Bound array access

#1322

· MrCookieeeee opened

on Apr 13, 2026

[BUG] Iverilog rejects a statement-labeled begin-end block written as label: begin ... end

#1321

· MrCookieeeee opened

on Apr 5, 2026

[BUG] Variable written in an always_ff block must not be written by any other process

#1317

· MrCookieeeee opened

on Mar 31, 2026

Cannot use conditional operator with string arguments

#1298

· chrisgelinek-rl opened

on Mar 1, 2026

Assignment patterns (IEEE 1800:2012, chapter 10.9)

#1294

· dettus opened

on Jan 30, 2026

Assertion failed: (net), function ivl_nexus_ptrs, file t-dll-api.cc, line 1791.

#1291

· shirriff opened

on Jan 7, 2026

command file read with LF fails

#1288

· aviadb opened

on Nov 27, 2025

Signal declaration after use not supported

#1287

· MichaelBell opened

on Nov 14, 2025