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@Kuree
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@Kuree Kuree commented Jun 15, 2018

When hls depth is 1, using 16-bit data width converter to upscale causes problems, as we observed yesterday. This PR removes data width converter and set dma width to 1, which allows the hwacc test to run successfully.

My guess to the bug is that when the data size streamed in is not an even number, upscaling from 1 to 2 has some padding issue.

Tested applications with depth==1 and depth ==3.

@stevenbell
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There's actually a similar problem I found a few days ago - suppose the input depth is 2 (1 16-bit pixel per cycle) and the output depth is 3 (1 24-bit RGB pixel per cycle). If we downconvert the output to 2 bytes/cycle, we end up stalling the pipeline for 1/3 of the cycles, which is really bad. A better algorithm would be to find the next power of 2 greater or equal to the output size, and convert to that.

We can fix that separately, or just roll it into this PR.

@stevenbell
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Can we go ahead and change this to use the next larger power of 2 when the width doesn't match? It looks like this just requires changing the depth = 2 (lines 121 and 134) and the corresponding part in the tcl file (line 617).

@Kuree
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Kuree commented Jul 1, 2018

I will do that once I finish the align HLS part.

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2 participants