[TTL] Add block transfer optimization framework with layout analysis #166
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Analyzes tensor layouts to select optimal DMA strategies: - FullyContiguous (row-major + interleaved): single noc_async_read/write - RowContiguous (row-major + sharded): per-row transfers (TODO: #118) - TileContiguous (tiled): per-tile noc_async_read_tile (current default) New files: - LayoutUtils.h/cpp: ContiguityLevel enum, analyzeLayoutContiguity() - block_transfers.mlir: tests for tiled and row-major layouts The lowering inspects TTNNLayoutAttr to determine if tensors use tiles or scalar elements, then dispatches to the appropriate transfer strategy.
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What?
Adds layout-aware transfer optimization to TTL-to-TTKernel lowering. The lowering analyzes tensor layouts and selects optimal DMA strategies based on data contiguity.
Why?
Block transfers (
noc_async_read/noc_async_write) are more efficient than tile-by-tile transfers for row-major data. This enables faster transfers when data is contiguous in memory.How?
Introduces a
ContiguityLevelclassification:The lowering inspects
TTNNLayoutAttrto determine if the tensor uses tiles or scalar elements, then dispatches to the appropriate transfer strategy.Deferred
How to Test?
Checklist: