Add support for page size > max prefetch cmd size for interleaved buffers #17677
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sagarwalTT
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| const uint32_t pcie_alignment = hal.get_alignment(HalMemType::HOST); | ||
| uint32_t mem_alignment = 0; | ||
| if (buffer.is_dram()) { | ||
| mem_alignment = hal.get_alignment(HalMemType::DRAM); |
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beyond the scope of this change, but buffer should return the hal memory type of the buffer to avoid mess like this
| TT_ASSERT(buffer.is_l1()); | ||
| mem_alignment = hal.get_alignment(HalMemType::L1); | ||
| } | ||
| while (partial_page_size % pcie_alignment != 0 || partial_page_size % mem_alignment != 0) { |
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this should be calculated explicitly not in a loop. hal could be improved to generate "max_alignment" during init so this doesn't have to get re-calculated
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#16861
This PR adds support for interleaved buffers to have page sizes which are greater than the max prefetch command size.
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