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Generic development topologies can reference core id outside of the range
of the number of DSP cores the device might have.
Product families have different number of cores, for example:
TGL has 4, TGL-H has 2, ADL has 4, ADL-S has 2, etc
The development topologies are tuned for the higher end devices and in this
case they will fail on DSP with less number of cores.

} else if (pipeline->core > sdev->num_cores - 1) {
dev_dbg(scomp->dev, "core id %d is out of range, changing it to %d\n",
pipeline->core, sdev->num_cores ? (sdev->num_cores - 1) : 0);
pipeline->core = sdev->num_cores ? (sdev->num_cores - 1) : 0;
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Im ok with this, although Id prefer switching all pipelines with invalid cores IDs to run on core 0 instead of Core N

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@ranj063, OK, I will move them to core0 and change the dev_dbg() to dev_info() to be visible in logs for us to decide if we need to address something or not.

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@ranj063 @ujfalusi you are the master, I'm ok with core0 as well, although I worry this allows topology develops to slip in bad topologies (as kernel driver is the primary end2end test bed when making topology changes). So a fatal error would be very useful to raise for tplg developers. But not blocking on this.

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We will print in info level to raise awareness, but at the same time I don't think it is better to have a back and forth to get a working system (does not work -> set 0x20 in sof_debug -> new topology for testing -> user test -> sof_debug kept until sof-bin release)

ranj063
ranj063 previously approved these changes Nov 20, 2025
kv2019i
kv2019i previously approved these changes Nov 21, 2025
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Minor notes and an opinion about whether this should be adjusted or an error. But nothing blocking.

} else if (pipeline->core > sdev->num_cores - 1) {
dev_dbg(scomp->dev, "core id %d is out of range, changing it to %d\n",
pipeline->core, sdev->num_cores ? (sdev->num_cores - 1) : 0);
pipeline->core = sdev->num_cores ? (sdev->num_cores - 1) : 0;
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@ranj063 @ujfalusi you are the master, I'm ok with core0 as well, although I worry this allows topology develops to slip in bad topologies (as kernel driver is the primary end2end test bed when making topology changes). So a fatal error would be very useful to raise for tplg developers. But not blocking on this.

@ujfalusi ujfalusi dismissed stale reviews from kv2019i and ranj063 via 5a54b1d November 21, 2025 12:44
@ujfalusi ujfalusi force-pushed the peter/sof/pr/validate_core_id branch from 4dc8b84 to 5a54b1d Compare November 21, 2025 12:44
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Changes since v1:

  • typo fixed in first patch commit
  • Second patch's commit to include Intel as it is a generic code
  • move out of range core id to core 0
  • print as dev_info() about the core id override to be visible in kernel log.

} else if (pipeline->core > sdev->num_cores - 1) {
dev_info(scomp->dev, "out of range core id for %s, moving it %d -> 0\n",
swidget->widget->name, pipeline->core);
pipeline->core = 0;
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PRIMARY instead of 0?

@ujfalusi ujfalusi force-pushed the peter/sof/pr/validate_core_id branch 2 times, most recently from cc9b22a to 1c47651 Compare November 24, 2025 10:44
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Changes since v2:

  • use SOF_DSP_PRIMARY_CORE instead of 0 when overriding the out of range core id

…ipelines

SOF_DBG_DISABLE_MULTICORE is handled for swidgets in topology.c but the
pipeline's core is not changed to primary core if the flag is set.

Check the flag and if it is set, force the pipeline core to primary core.

Cc: [email protected] # 6.7+
Signed-off-by: Peter Ujfalusi <[email protected]>
…es of the DSP

Generic development topologies can reference core id outside of the range
of the number of DSP cores the device might have.
Product families have different number of cores, for example:
Intel TGL has 4, TGL-H has 2, ADL has 4, ADL-S has 2, etc
The development topologies are tuned for the higher end devices and in this
case they will fail on DSP with less number of cores.

Override the out of range core id from topology to primary core and inform
the user about it.

Signed-off-by: Peter Ujfalusi <[email protected]>
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4 participants