riscv: fix RV64 CSR compilation#4865
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`RiscvThreadIdProvider::running_thread_id()` was `unimplemented!()` for every target except riscv32 (a mock branch), so any rv64 use of `SingleThreadValue` / deferred calls panicked at runtime. This path had simply never been exercised (no rv64 board existed). The implementation -- read `mhartid`, load the `_trap_handler_active` symbol address, read a `usize` -- is XLEN-agnostic, so widen its cfg to cover rv64 as well. Same character as the RV64 CSR compile fixes (tock#4865): an unexercised RV64 path. Standalone and cherry-pickable. Re tock#2332. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> Signed-off-by: Siju Kurian <sijukurian@gmail.com>
bradjc
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Jun 8, 2026
jrvanwhy
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Jun 8, 2026
The RV64 cfg-gating in arch/riscv/src/csr/mod.rs was never compiled for a
riscv64 target (no RV64 board existed) and had two bugs that stopped the
`riscv` crate building for riscv64:
1. `pmpcfg0` was gated `cfg(not(target_arch = "riscv64"))`, removing it on
RV64. RV64 uses the even-indexed config registers (pmpcfg0, 2, 4, ...,
14); pmpcfg0 is the first of these and must be present. The const CSR
initializer and all three `pmpconfig_{get,set,modify}` accessors already
reference `pmpcfg0` unconditionally, so the missing field caused
E0560/E0609.
2. `read_cycle_counter()` on RV64 returned the `usize` result of
`CSR.mcycle.read(...)` where `u64` is expected (E0308); added a cast.
Also split the riscv32-only CSR id imports (the high-half and odd-indexed
registers) into their own `cfg(not(target_arch = "riscv64"))` `use` block, so
the riscv64 build stays warning-free without an allow(unused_imports).
Found while bringing up Tock on a 64-bit RISC-V core (re tock#2332).
Signed-off-by: Siju Kurian <sijukurian@gmail.com>
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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bradjc
approved these changes
Jun 9, 2026
jrvanwhy
approved these changes
Jun 9, 2026
siju-felsite
pushed a commit
to siju-felsite/tock
that referenced
this pull request
Jun 10, 2026
`RiscvThreadIdProvider::running_thread_id()` was `unimplemented!()` for every target except riscv32 (a mock branch), so any rv64 use of `SingleThreadValue` / deferred calls panicked at runtime. This path had simply never been exercised (no rv64 board existed). The implementation -- read `mhartid`, load the `_trap_handler_active` symbol address, read a `usize` -- is XLEN-agnostic, so widen its cfg to cover rv64 as well. Same character as the RV64 CSR compile fixes (tock#4865): an unexercised RV64 path. Standalone and cherry-pickable. Re tock#2332. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> Signed-off-by: Siju Kurian <sijukurian@gmail.com>
This was referenced Jun 10, 2026
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Pull Request Overview
The RV64
cfg-gating inarch/riscv/src/csr/mod.rswas never compiled for a riscv64 target (no RV64 board exists yet), which hid two bugs that stopped theriscvcrate from building for riscv64:pmpcfg0was gatedcfg(not(target_arch = "riscv64")), removing it on RV64. RV64 uses the even-indexed PMP config registers (pmpcfg0,pmpcfg2, …,pmpcfg14);pmpcfg0is the first of these and must be present. The const CSR initializer and all threepmpconfig_{get,set,modify}accessors already referencepmpcfg0unconditionally, so the missing field causedE0560/E0609.read_cycle_counter()on RV64 returned theusizeresult ofCSR.mcycle.read(...)whereu64is expected (E0308); added an explicit cast.This also annotates the CSR id import with
cfg_attr(target_arch = "riscv64", allow(unused_imports)), since the high-half (*H) and odd-indexedPMPCFG*registers arecfg'd out on riscv64.The rv32 code paths are untouched. This is groundwork toward #2332 (64-bit RISC-V support) and is independent of any board or the remaining startup/trap/context-switch asm.
Testing Strategy
Built
arch/riscv(and a thin downstream rv64 crate that depends on it) forriscv64imac-unknown-none-elf— it now compiles cleanly and warning-free, whereas before it failed with the errors above.make prepush(format-check, clippy, syntax, licensecheck) passes clean. The rv32cfgpaths are unchanged, so existing RISC-V boards are unaffected.TODO or Help Wanted
None — this is a standalone build-correctness fix.
Documentation Updated
/docs, or no updates are required.Formatting
make prepush.AI Use
This change was developed with the assistance of an AI coding assistant (Claude / Claude Code). The two compile-error fixes and the
cfg_attr(allow(unused_imports))annotation were AI-generated and then reviewed before submission.