xilinx
Here are 716 public repositories matching this topic...
Must-have verilog systemverilog modules
- 
            Updated
            Aug 2, 2025 
- Verilog
Brevitas: neural network quantization in PyTorch
- 
            Updated
            Oct 28, 2025 
- Python
32-bit Superscalar RISC-V CPU
- 
            Updated
            Sep 18, 2021 
- Verilog
An abstraction library for interfacing EDA tools
- 
            Updated
            Oct 31, 2025 
- Python
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
- 
            Updated
            Sep 14, 2023 
- Batchfile
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
- 
            Updated
            Jul 7, 2020 
- SystemVerilog
Bus bridges and other odds and ends
- 
            Updated
            Apr 14, 2025 
- Verilog
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
- 
            Updated
            Jul 30, 2025 
- VHDL
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
- 
            Updated
            Jan 12, 2023 
- C
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
- 
            Updated
            Jan 5, 2019 
- VHDL
Improve this page
Add a description, image, and links to the xilinx topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the xilinx topic, visit your repo's landing page and select "manage topics."