[#2391] test: cover mret without U-mode

Author: carlosqwqqwq

tests/unit/test_riscv.c

@@ -55,6 +55,30 @@ static void test_riscv64_nop(void)
     OK(uc_close(uc));
 }
 
+static void test_riscv64_mret_without_u(void)
+{
+    uc_engine *uc;
+    const char code[] = "\x73\x00\x20\x30"; // mret
+    uint64_t misa;
+    uint64_t mstatus = 3ULL << 11;
+    uint64_t mepc = code_start + sizeof(code) - 1;
+
+    OK(uc_open(UC_ARCH_RISCV, UC_MODE_RISCV64, &uc));
+    OK(uc_mem_map(uc, code_start, code_len, UC_PROT_ALL));
+    OK(uc_mem_write(uc, code_start, code, sizeof(code) - 1));
+    OK(uc_reg_read(uc, UC_RISCV_REG_MISA, &misa));
+    misa &= ~(1ULL << 20);
+    OK(uc_reg_write(uc, UC_RISCV_REG_MISA, &misa));
+    OK(uc_reg_write(uc, UC_RISCV_REG_MSTATUS, &mstatus));
+    OK(uc_reg_write(uc, UC_RISCV_REG_MEPC, &mepc));
+
+    OK(uc_emu_start(uc, code_start,
+                    code_start + sizeof(code) - 1, 0, 0));
+    OK(uc_reg_read(uc, UC_RISCV_REG_MSTATUS, &mstatus));
+    TEST_CHECK(((mstatus >> 11) & 3) == 3);
+    OK(uc_close(uc));
+}
+
 static void test_riscv32_until_pc_update(void)
 {
     uc_engine *uc;
@@ -911,6 +935,7 @@ static void test_riscv_priv(void)
 TEST_LIST = {
     {"test_riscv32_nop", test_riscv32_nop},
     {"test_riscv64_nop", test_riscv64_nop},
+    {"test_riscv64_mret_without_u", test_riscv64_mret_without_u},
     {"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update},
     {"test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update},
     {"test_riscv64_until_at_page_end", test_riscv64_until_at_page_end},