riscv: gate counter CSRs on mcounteren at every priv version

[carlosqwqqwq]

Fixes #2387

Change

Remove the version-based early-success branch from qemu/target/riscv/csr.c:ctr() so the existing mcounteren and scounteren checks apply to every supported privileged-spec version. M-mode access remains unchanged.

Validation

• Rebased onto dev.
• Added test_riscv64_mcounteren in tests/unit/test_riscv.c.
• The public u009 witness reaches UC_ERR_EXCEPTION on the gated U-mode read.
• The M-mode legal-access control remains functional.

Public reproducer:
https://github.com/carlosqwqqwq/unicorn-riscv-repros/tree/main/u009

Verify that M-mode counter access is unaffected, S/U-mode accesses are gated by mcounteren/scounteren, and existing counter and CSR tests remain unchanged.

[carlosqwqqwq]

Thank you very much for taking the time to review this PR. We have rebased it onto dev and added a focused unit test for the counter-access behavior. Could you please let us know what further code, test, or PR changes you would recommend? We will gladly adjust the patch to match the project guidelines.