riscv: gate fsgnj.d/fmv.d on FPU and D extension

[carlosqwqqwq]

Fixes #2388

Problem

trans_fsgnj_d lacks REQUIRE_FPU and REQUIRE_EXT(ctx, RVD), so fsgnj.d/fmv.d retire on CPU models without F/D (e.g. SiFive E51) instead of raising an illegal-instruction trap.

Change

qemu/target/riscv/insn_trans/trans_rvd.inc.c trans_fsgnj_d: add REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); at the top, matching every other D-extension translation in the same file.

The focused unit test is test_riscv64_fsgnj_d_cpu_feature in tests/unit/test_riscv.c; the public u020 runner is linked below.

Validation

• Rebased onto dev.
• Added focused E51 coverage in tests/unit/test_riscv.c.
• The public E51 witness traps without F/D.
• The D-enabled control remains legal and the existing RISC-V test suite passes.

Public reproducer:
https://github.com/carlosqwqqwq/unicorn-riscv-repros/tree/main/u020

[carlosqwqqwq]

Thank you very much for taking the time to review this PR. We have rebased it onto dev, added the required feature checks, and added focused coverage for an RV64 CPU without the D extension. Could you please let us know what further code, test, or PR changes you would recommend? We will gladly adjust the patch to match the project guidelines.