fix: riscv PC advance for compressed instructions and fetch faults - #2400
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cpu_handle_exception unconditionally does env->pc += 4 for RISC-V. That corrupts the PC for 16-bit compressed instructions and for instruction access/page faults, where env->pc already holds the faulting address and must not be advanced. Move the logic into a RISC-V helper, riscv_cpu_prepare_exception_pc(), which mirrors the trap state riscv_cpu_do_interrupt would set up: - load mbadaddr from badaddr for every address-bearing exception so the UC_HOOK_INTR callback can inspect the faulting address - advance the PC by the real instruction size (2 or 4 bytes, from the low two opcode bits) for execution-time exceptions - leave the PC untouched for INST_ADDR_MIS / INST_ACCESS_FAULT / INST_PAGE_FAULT Extract the address-bearing exception list into a shared riscv_cpu_exception_has_badaddr() predicate used by both do_interrupt and the new helper, instead of duplicating the switch.
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Closing this as superseded by #2384. That PR preserves the faulting PC while the hook runs and advances to the translator-recorded next PC only after a handled One part is missing from #2384. For instruction, load, and store address faults, RISC-V places the faulting address in I built that commit with RISC-V enabled. All 30 tests from #2384 pass. |
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cpu_handle_exceptionunconditionally doesenv->pc += 4for RISC-V. This corrupts the PC for 16-bit compressed instructions and for instruction access/page faults (whereenv->pcalready holds the faulting address and must not be advanced). It also leaves the faulting address unavailable toUC_HOOK_INTRcallbacks.Changes:
env->pcby the real instruction size (2 or 4 bytes, determined by the low two opcode bits) for execution-time exceptions.INST_ADDR_MIS,INST_ACCESS_FAULT,INST_PAGE_FAULT.riscv_cpu_do_interruptand setenv->mbadaddr = env->badaddrfor every address-bearing exception, so the callback can recover from e.g. PMP faults.Verified by booting a RISC-V firmware under Unicorn whose syscall/return path is full of compressed instructions and relies on lazy PMP fault recovery.