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Merged
merged 13 commits into from
Aug 8, 2025
Merged

Upgrading to Yosys v0.55 and Updating Slang #3221

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670362d
Slang now reads the primitives file and the user design verilog in th…
loglav03 Aug 1, 2025
98a1851
Exposed the vtr_primitives.v path to yosys-slang and disabled the yos…
loglav03 Aug 1, 2025
2d9efb0
Updating yosys-slang to most recent version
loglav03 Aug 1, 2025
4168620
Fixing read verilog setup in synthesis.tcl
loglav03 Aug 1, 2025
344f640
Upgrade yosys submodule to v0.55
loglav03 Aug 1, 2025
eb0f8e7
Added missing top modules in system verilog regression test to top_ma…
loglav03 Aug 1, 2025
6ddec3d
Updating golden results for parmys basic test
loglav03 Aug 1, 2025
9f1343c
Updating golden results for nand and nor parmys benchmarks
loglav03 Aug 5, 2025
9315af7
Added koios benchmarks to synthesis top_map array map. Prevented top …
loglav03 Aug 5, 2025
564a8e3
Removed patch_slang.cmake
loglav03 Aug 6, 2025
1b3b4a3
Removed commented out code in synthesis.tcl
loglav03 Aug 6, 2025
dcde9d4
Merge branch 'master' into yosys_and_slang_update_v0.55
AlexandreSinger Aug 7, 2025
629458d
Merge branch 'master' into yosys_and_slang_update_v0.55
AlexandreSinger Aug 8, 2025
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5 changes: 0 additions & 5 deletions libs/EXTERNAL/CMakeLists.txt
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Expand Up @@ -102,11 +102,6 @@ if (${WITH_PARMYS})
yosys-slang
SOURCE_DIR ${SLANG_SRC_DIR}
BINARY_DIR ${SLANG_BUILD_DIR}

#Disabling UndrivenPass in slang_frontend.cc
PATCH_COMMAND
${CMAKE_COMMAND} -E echo "Patching slang_frontend.cc to disable UndrivenPass" &&
${CMAKE_COMMAND} -DIN=${SLANG_FE} -P ${CMAKE_CURRENT_SOURCE_DIR}/patch_slang.cmake

CONFIGURE_COMMAND ""

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18 changes: 0 additions & 18 deletions libs/EXTERNAL/patch_slang.cmake
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This file was deleted.

2 changes: 1 addition & 1 deletion libs/EXTERNAL/yosys
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Submodule yosys updated 119 files
2 changes: 1 addition & 1 deletion libs/EXTERNAL/yosys-slang
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Submodule yosys-slang updated 22 files
+16 −51 .github/workflows/build-and-test.yaml
+74 −0 .github/workflows/coverage.yaml
+21 −0 CMakeLists.txt
+4 −0 cmake/AddCompileLinkOptions.cmake
+10 −2 cmake/GitRevision.cmake
+11 −3 src/builder.cc
+9 −0 src/cases.cc
+50 −19 src/cases.h
+0 −5 src/diag.cc
+0 −1 src/diag.h
+3 −2 src/procedural.cc
+38 −10 src/slang_frontend.cc
+2 −2 src/slang_frontend.h
+30 −2 tests/CMakeLists.txt
+16 −1 tests/unit/latch.ys
+60 −0 tests/unit/latch_addressing.ys
+8 −0 tests/various/ignore_asserts.ys
+22 −0 tests/various/issue208.ys
+40 −1 tests/various/regress.sv
+1 −1 tests/various/unknown_cells.ys
+1 −1 third_party/fmt
+1 −1 third_party/slang
2 changes: 1 addition & 1 deletion parmys/regression_test/benchmark/task/freecores/synthesis_result.json
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Expand Up @@ -483,7 +483,7 @@
"Average Path": 3,
"Estimated LUTs": 4777,
"Total Node": 1957,
"Wires": 5592,
"Wires": 5594,
"Wire Bits": 10106,
"Public Wires": 240,
"Public Wire Bits": 240,
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6 changes: 3 additions & 3 deletions parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json
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Expand Up @@ -95,21 +95,21 @@
"test_name": "and/replicate_and_int_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"and/replicate_and_ultra_wide/no_arch": {
"test_name": "and/replicate_and_ultra_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"and/replicate_and_wide/no_arch": {
"test_name": "and/replicate_and_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"DEFAULT": {
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6 changes: 3 additions & 3 deletions parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json
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Expand Up @@ -94,21 +94,21 @@
"test_name": "nand/replicate_nand_int_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"nand/replicate_nand_ultra_wide/no_arch": {
"test_name": "nand/replicate_nand_ultra_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"nand/replicate_nand_wide/no_arch": {
"test_name": "nand/replicate_nand_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"DEFAULT": {
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6 changes: 3 additions & 3 deletions parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json
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Expand Up @@ -100,21 +100,21 @@
"test_name": "nor/replicate_nor_int_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"nor/replicate_nor_ultra_wide/no_arch": {
"test_name": "nor/replicate_nor_ultra_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"nor/replicate_nor_wide/no_arch": {
"test_name": "nor/replicate_nor_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"DEFAULT": {
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6 changes: 3 additions & 3 deletions parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json
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Expand Up @@ -95,21 +95,21 @@
"test_name": "or/replicate_or_int_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"or/replicate_or_ultra_wide/no_arch": {
"test_name": "or/replicate_or_ultra_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"or/replicate_or_wide/no_arch": {
"test_name": "or/replicate_or_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"DEFAULT": {
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6 changes: 3 additions & 3 deletions parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json
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Expand Up @@ -54,21 +54,21 @@
"test_name": "xnor/replicate_xnor_int_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"xnor/replicate_xnor_ultra_wide/no_arch": {
"test_name": "xnor/replicate_xnor_ultra_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"xnor/replicate_xnor_wide/no_arch": {
"test_name": "xnor/replicate_xnor_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"xnor/xnor_indexed_port/no_arch": {
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6 changes: 3 additions & 3 deletions parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json
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Expand Up @@ -51,21 +51,21 @@
"test_name": "xor/replicate_xor_int_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"xor/replicate_xor_ultra_wide/no_arch": {
"test_name": "xor/replicate_xor_ultra_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"xor/replicate_xor_wide/no_arch": {
"test_name": "xor/replicate_xor_wide/no_arch",
"exit": 1,
"errors": [
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755."
]
},
"xor/xor_indexed_port/no_arch": {
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18 changes: 9 additions & 9 deletions parmys/regression_test/benchmark/task/koios/koios_medium/synthesis_result.json
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Expand Up @@ -565,15 +565,15 @@
"Average Path": 5,
"Estimated LUTs": 15571,
"Total Node": 4795,
"Wires": 45931,
"Wire Bits": 49668,
"Wires": 45932,
"Wire Bits": 49669,
"Public Wires": 5161,
"Public Wire Bits": 5161,
"Total Cells": 42904,
"Total Cells": 42905,
"MUX": 22203,
"XOR": 15,
"OR": 2990,
"AND": 2640,
"AND": 2641,
"NOT": 255,
"DFFs": [
"$_DFF_P_ 11798"
Expand Down Expand Up @@ -1221,14 +1221,14 @@
"Average Path": 4,
"Estimated LUTs": 13223,
"Total Node": 5602,
"Wires": 28994,
"Wire Bits": 50685,
"Wires": 28995,
"Wire Bits": 50688,
"Public Wires": 3999,
"Public Wire Bits": 3999,
"Total Cells": 42439,
"Total Cells": 42435,
"MUX": 11266,
"XOR": 3492,
"OR": 5746,
"OR": 5742,
"AND": 8418,
"NOT": 3193,
"DFFs": [
Expand Down Expand Up @@ -1457,7 +1457,6 @@
"Resizing cell port systolic_pe_matrix.pe0_2.in_b from 8 bits to 19 bits.",
"Resizing cell port systolic_pe_matrix.pe0_1.in_b from 8 bits to 19 bits.",
"Resizing cell port systolic_pe_matrix.pe0_0.in_b from 8 bits to 19 bits.",
"Ignoring module matmul_16x16_systolic because it contains processes (run 'proc' command first).",
"Ignoring module top because it contains processes (run 'proc' command first).",
"Ignoring module activation because it contains processes (run 'proc' command first).",
"Ignoring module pool because it contains processes (run 'proc' command first).",
Expand All @@ -1470,6 +1469,7 @@
"Ignoring module processing_element because it contains processes (run 'proc' command first).",
"Ignoring module systolic_data_setup because it contains processes (run 'proc' command first).",
"Ignoring module output_logic because it contains processes (run 'proc' command first).",
"Ignoring module matmul_16x16_systolic because it contains processes (run 'proc' command first).",
"Wire processing_element.\\chainin [63] is used but has no driver.",
"Wire processing_element.\\chainin [62] is used but has no driver.",
"Wire processing_element.\\chainin [61] is used but has no driver.",
Expand Down
38 changes: 19 additions & 19 deletions parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json
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Expand Up @@ -169,8 +169,8 @@
"Average Path": 3,
"Estimated LUTs": 28720,
"Total Node": 16803,
"Wires": 58018,
"Wire Bits": 81586,
"Wires": 58019,
"Wire Bits": 81589,
"Public Wires": 8454,
"Public Wire Bits": 8454,
"Total Cells": 42029,
Expand Down Expand Up @@ -464,7 +464,7 @@
"Estimated LUTs": 22752,
"Total Node": 5094,
"Wires": 24045,
"Wire Bits": 37590,
"Wire Bits": 37311,
"Public Wires": 5228,
"Public Wire Bits": 5228,
"Total Cells": 24019,
Expand Down Expand Up @@ -670,15 +670,15 @@
"Average Path": 5,
"Estimated LUTs": 16387,
"Total Node": 6499,
"Wires": 57055,
"Wire Bits": 60792,
"Wires": 57056,
"Wire Bits": 60793,
"Public Wires": 2053,
"Public Wire Bits": 2053,
"Total Cells": 51015,
"Total Cells": 51016,
"MUX": 26043,
"XOR": 15,
"OR": 2989,
"AND": 2640,
"AND": 2641,
"NOT": 255,
"DFFs": [
"$_DFF_P_ 14486"
Expand Down Expand Up @@ -1227,14 +1227,14 @@
"Average Path": 5,
"Estimated LUTs": 13699,
"Total Node": 7769,
"Wires": 29721,
"Wire Bits": 41696,
"Wires": 29722,
"Wire Bits": 41699,
"Public Wires": 3147,
"Public Wire Bits": 3147,
"Total Cells": 33385,
"Total Cells": 33386,
"MUX": 8974,
"XOR": 624,
"OR": 4219,
"OR": 4220,
"AND": 5530,
"NOT": 1685,
"DFFs": [
Expand Down Expand Up @@ -1335,14 +1335,14 @@
"Average Path": 4,
"Estimated LUTs": 13223,
"Total Node": 5602,
"Wires": 28999,
"Wire Bits": 50657,
"Wires": 29005,
"Wire Bits": 50691,
"Public Wires": 3999,
"Public Wire Bits": 3999,
"Total Cells": 42389,
"Total Cells": 42423,
"MUX": 11266,
"XOR": 3492,
"OR": 5695,
"OR": 5729,
"AND": 8419,
"NOT": 3193,
"DFFs": [
Expand Down Expand Up @@ -1467,14 +1467,14 @@
"Average Path": 8,
"Estimated LUTs": 37160,
"Total Node": 11295,
"Wires": 46405,
"Wire Bits": 117654,
"Wires": 46404,
"Wire Bits": 117642,
"Public Wires": 1513,
"Public Wire Bits": 1513,
"Total Cells": 70238,
"Total Cells": 70240,
"MUX": 22023,
"XOR": 1594,
"OR": 17552,
"OR": 17554,
"AND": 10572,
"NOT": 5150,
"DFFs": [
Expand Down
16 changes: 8 additions & 8 deletions parmys/regression_test/benchmark/task/syntax/synthesis_result.json
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Expand Up @@ -2924,8 +2924,8 @@
"Average Path": 4,
"Estimated LUTs": 101,
"Total Node": 67,
"Wires": 212,
"Wire Bits": 268,
"Wires": 213,
"Wire Bits": 269,
"Public Wires": 177,
"Public Wire Bits": 177,
"Total Cells": 145,
Expand Down Expand Up @@ -2964,8 +2964,8 @@
"Average Path": 5,
"Estimated LUTs": 25938,
"Total Node": 34130,
"Wires": 76077,
"Wire Bits": 84563,
"Wires": 76078,
"Wire Bits": 84564,
"Public Wires": 75169,
"Public Wire Bits": 75169,
"Total Cells": 59068,
Expand Down Expand Up @@ -4048,8 +4048,8 @@
"Average Path": 4,
"Estimated LUTs": 101,
"Total Node": 33,
"Wires": 103,
"Wire Bits": 168,
"Wires": 104,
"Wire Bits": 169,
"Public Wires": 71,
"Public Wire Bits": 71,
"Total Cells": 111,
Expand Down Expand Up @@ -4086,8 +4086,8 @@
"Average Path": 4,
"Estimated LUTs": 33,
"Total Node": 33,
"Wires": 103,
"Wire Bits": 168,
"Wires": 104,
"Wire Bits": 169,
"Public Wires": 71,
"Public Wire Bits": 71,
"Total Cells": 111,
Expand Down
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