Now direct connection builder in tileable rr_graph supports any subtile index as the from_pin #3318

tangxifan · 2025-10-24T17:08:34Z

Description

This PR aims to enhance the direct connection builder of the tileable routing resource graph builder, with the following new feature:

It support any subtiles at any z in a tile as the starting point of a direct connection. Current direct builder requires the first subtile to be the starting point, which is very restrictive.

Related Issue

No issue is related. Stated in the description section.

Motivation and Context

Stated in the description section.

How Has This Been Tested?

All the existing tests passed.
Three new testcases have been added to the strong regression tests, each of which validate the new feature
- DSP and BRAM sub-tiles are stacked in the same tile. The starting point of direct connections come from the DSP (the 3rd sub-tile) and ends at the BRAMs (the 1st and 2nd sub-tiles)
- CLB, DSP and BRAM sub-tiles are stacked in the same tile. The starting of direction connections come from the DSP (the 2nd sub-tile) and ends at the BRAMs (the 3rd and 4th sub-tiles)
- CLB, DSP and BRAM sub-tiles are stacked in the same tile. The starting of direction connections come from the DSP (the 4th sub-tile) and ends at the BRAMs (the 2nd and 3rd sub-tiles)
Added 3 new architecture files and a blif benchmark to validate the DSP-to-RAM direct connections

Types of changes

Bug fix (change which fixes an issue)
New feature (change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

My change requires a change to the documentation
I have updated the documentation accordingly
I have added tests to cover my changes
All new and existing tests passed

…alidate the direct connections across subtiles

…ests

… connection for tileable rr_graph

…in the direct

tangxifan · 2025-10-24T17:49:21Z

@vaughnbetz This PR is ready for your review.

I notice this feature is missing for the regular rr_graph builder. We can add it if you want.

I have added @amin1377 as a potential reviewer.

vaughnbetz

Looks good, except it needs a Doxygen comment on a new utility function.

I also find the (true == swap) style odd, but if you really like it I'm not dogmatic on that.

Adding this to the default rr-graph builder is a good idea, so if you can do that it would be good.

Does any documentation need to be updated?

vaughnbetz · 2025-10-24T17:57:28Z

vpr/src/util/vpr_utils.h


 bool is_empty_type(t_physical_tile_type_ptr type);
 bool is_empty_type(t_logical_block_type_ptr type);
+std::vector<int> find_sub_tile_indices_by_port_name(t_physical_tile_type_ptr type, std::string_view port_name);


This should have a doxygen comment describing the function purpose, return type and parameters.

Code comments have been added.

vaughnbetz · 2025-10-24T17:57:53Z

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp

+                    int relative_ipin = UNDEFINED;
+                    if (clb_to_clb_directs[i].to_clb_pin_start_index
+                        > clb_to_clb_directs[i].to_clb_pin_end_index) {
+                        if (true == swap) {


Odd style. I'd just put
if (swap)

vaughnbetz · 2025-10-24T17:58:11Z

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp

+                        }
                    } else {
-                        relative_ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset;
+                        if (true == swap) {


Odd style. I'd use:
if (swap)

…or regular rr_graph generator

…s between subtiles

amin1377

Thanks, Xifan. I’d suggest adding the figure you included in the PR description to this document (Link)

amin1377 · 2025-10-24T18:41:55Z

vpr/src/util/vpr_utils.cpp

    return get_class_num_from_pin_physical_num(physical_type, pin_physical_num);
 }

+std::vector<int> find_sub_tile_indices_by_port_name(t_physical_tile_type_ptr type, std::string_view port_name) {


@tangxifan: I’m a little confused here. Let’s say I have a tile that has 5 subtiles of the same type. All of those subtiles would have the same port name… How would you get the index of a subtile then?

It will get all the indices of the subtiles as long as the subtile has a port in the required name. These subtiles can all be the starting point of a direct connection.

…et at tile-level (pin location)

…ting/vtr-verilog-to-routing into xt_tileable_direct_strong

tangxifan · 2025-10-24T21:04:38Z

@vaughnbetz Thank you for the quick feedback. I have addressed the code comments.

Now the regular rr_graph generator supports the direct connections across subtiles. New testcases have to added to validate the regular rr_graph generator.

vaughnbetz

One minor nit in a comment, but other than that looks good to go.

vaughnbetz · 2025-10-24T22:13:54Z

vpr/src/util/vpr_utils.h

 bool is_empty_type(t_logical_block_type_ptr type);

+/**
+ * @brief Returns the indices of sub tiles in a given physical type which contains the ports in a specified name. It will return all the sub tiles that contain the required port. Note that the sub tiles may be in different types


Minor nits: I think this should be:
"which contain the specified port name."
"Note that the sub tiles may be of different types"

tangxifan · 2025-10-24T22:33:21Z

Thanks, Xifan. I’d suggest adding the figure you included in the PR description to this document (Link)

Thanks @amin1377 Doc has been updated.

tangxifan · 2025-10-24T23:24:27Z

@vaughnbetz @amin1377 All the comments are addressed. CI is green. Please suggest if I can merge this PR.

vaughnbetz · 2025-10-24T23:50:20Z

Please go ahead and merge.VaughnOn Oct 24, 2025, at 7:24 PM, tangxifan ***@***.***> wrote:tangxifan left a comment (verilog-to-routing/vtr-verilog-to-routing#3318) @vaughnbetz @amin1377 All the comments are addressed. CI is green. Please suggest if I can merge this PR. —Reply to this email directly, view it on GitHub, or unsubscribe.You are receiving this because you were mentioned.Message ID: ***@***.***>

tangxifan added 16 commits October 23, 2025 17:04

[test] add a strong test where clb, dsp and bram in a same tile, to v…

85b82b1

…alidate the direct connections across subtiles

[test] deploy new test to strong reg test

1009339

[test] add new test

6672c7a

[test] add new arch from openfpga

9da2e46

[test] add new blif benchmark for tileable direct connection strong t…

83540ce

…ests

[test] add new example arch to validate tileable direct connections

90de0e8

[test] reorg tasks

615eb82

[test] deploy new tests to validate supertile with z_offset in direct…

da7c322

… connection for tileable rr_graph

[test] debug

cafdcd1

[test] debug

27d3040

[core] debug

6fc15ec

[core] now search all the sub tiles which contains the ports defined …

881255c

…in the direct

[core] syntax

df2a7de

[test] debug

2ea4ad0

[test] update golden

2107714

[test] add missing golden results

55ad286

github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code lang-netlist labels Oct 24, 2025

Merge branch 'master' into xt_tileable_direct_strong

1067e11

tangxifan changed the title ~~[WIP] Now direct connection builder in tileable rr_graph supports any subtile index as the from_pin~~ Now direct connection builder in tileable rr_graph supports any subtile index as the from_pin Oct 24, 2025

tangxifan requested review from amin1377 and vaughnbetz October 24, 2025 17:48

vaughnbetz requested changes Oct 24, 2025

View reviewed changes

tangxifan added 5 commits October 24, 2025 11:14

[core] add doxygen-style comments to vpr utility function

e8ebafb

[core] simplify swap in if condition

d93f036

Merge branch 'master' into xt_tileable_direct_strong

97c7bc8

[test] add arch file to validate direct connections across subtiles f…

9baa66e

…or regular rr_graph generator

[test] add new testcases for strong reg tests about direct connection…

dcbe115

…s between subtiles

amin1377 approved these changes Oct 24, 2025

View reviewed changes

tangxifan added 7 commits October 24, 2025 13:24

[core] fixed the bug where IPIN coordinate does not consider pin offs…

bd589a9

…et at tile-level (pin location)

[core] should sit with root location for IPIN

2ffbff3

[core] debug

68d6e23

[core] debug

e11a7ee

[core] debug

daa754f

[test] update golden

4c9b8fa

Merge branch 'xt_tileable_direct_strong' of github.com:verilog-to-rou…

8d3ab0e

…ting/vtr-verilog-to-routing into xt_tileable_direct_strong

[doc] add examples

aa76d71

github-actions bot added the docs Documentation label Oct 24, 2025

[doc] typo

35eeb2e

vaughnbetz approved these changes Oct 24, 2025

View reviewed changes

[core] typo

07e8b6f

[doc] typo

7ffcdf0

tangxifan merged commit 0502b83 into master Oct 24, 2025
30 checks passed

tangxifan deleted the xt_tileable_direct_strong branch October 24, 2025 23:59

tangxifan mentioned this pull request Oct 25, 2025

Update VTR to latest & Add strong testcases to validate direct connections across subtiles lnis-uofu/OpenFPGA#2208

Merged

Now direct connection builder in tileable rr_graph supports any subtile index as the from_pin #3318

Now direct connection builder in tileable rr_graph supports any subtile index as the from_pin #3318

Uh oh!

Conversation

tangxifan commented Oct 24, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Description

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

Checklist:

Uh oh!

tangxifan commented Oct 24, 2025

Uh oh!

vaughnbetz left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

amin1377 left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

tangxifan commented Oct 24, 2025

Uh oh!

vaughnbetz left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

tangxifan commented Oct 24, 2025

Uh oh!

tangxifan commented Oct 24, 2025

Uh oh!

vaughnbetz commented Oct 24, 2025 via email

Uh oh!

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

tangxifan commented Oct 24, 2025 •

edited

Loading