rcar_gen5: Rebase X5H support on top of 4.10

.gitignore

@@ -13,3 +13,8 @@
 !.gitignore
 !.github
 !.devcontainer
+.cproject
+cscope.*
+.project
+*.swp
+.vscode

core/arch/arm/plat-rcar_gen5/conf.mk

@@ -0,0 +1,41 @@
+PLATFORM_FLAVOR ?= X5H
+include core/arch/arm/cpu/cortex-armv8-0.mk
+
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
+$(call force,CFG_SCIF,y)
+$(call force,CFG_GIC,y)
+$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
+$(call force,CFG_CORE_ARM64_PA_BITS,36)
+# Disable core ASLR for two reasons:
+# 1. There is no source for ALSR seed, as Rcar platform
+# does not provide DTB to OP-TEE. Also, there is no
+# publically available documentation on integrated
+# hardware RNG, so we can't use it either.
+# 2. OP-TEE crashes during boot with enabled CFG_CORE_ASLR.
+$(call force,CFG_CORE_ASLR,n)
+$(call force,CFG_ARM64_core,y)
+$(call force,CFG_WITH_LPAE,y)
+ifeq ($(PLATFORM_FLAVOR), X5H)
+$(call force,CFG_RCAR_GEN5, y)
+endif
+
+CFG_ARM_GICV3 ?= y
+CFG_CRYPTO_WITH_CE ?= n
+CFG_TZDRAM_START ?= 0x8C300000
+CFG_TZDRAM_SIZE  ?= 0x02000000
+supported-ta-targets = ta_arm64
+CFG_DT ?= n
+CFG_WITH_SOFTWARE_PRNG ?= y
+CFG_TEE_CORE_DEBUG ?= n
+
+ifeq ($(CFG_RCAR_GEN5), y)
+# 1xx - for SCIFxx
+# 2xx - for HSCIFxx
+CFG_RCAR_UART ?= 200
+$(call force,CFG_CORE_CLUSTER_SHIFT,2) #log2(2) = 4 --> 4(cores/per cluster)
+$(call force,CFG_TEE_CORE_NB_CORE,32)
+CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE)
+CFG_MMAP_REGIONS ?= 21
+endif
+

core/arch/arm/plat-rcar_gen5/link.mk

@@ -0,0 +1,5 @@
+include core/arch/arm/kernel/link.mk
+
+SRECFLAGS ?= --srec-forceS3 --adjust-vma=$(CFG_TZDRAM_START)
+
+all: $(link-out-dir)/tee.srec

core/arch/arm/plat-rcar_gen5/main.c

@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2025, Renesas Electronics Corporation.
+ */
+
+#include <console.h>
+#include <crypto/crypto.h>
+#include <kernel/boot.h>
+#include <kernel/panic.h>
+#include <mm/core_memprot.h>
+#include <platform_config.h>
+#include <stdint.h>
+#include <drivers/hscif.h>
+#include <drivers/gic.h>
+#include <sm/optee_smc.h>
+#include <tee/entry_fast.h>
+#include <tee/tee_cryp_utl.h>
+
+#include "rcar_log_func.h"
+#include "rcar-common.h"
+
+#ifdef MEMORY1_BASE
+register_phys_mem_pgdir(MEMORY1_TYPE, MEMORY1_BASE, MEMORY1_SIZE);
+#endif
+#ifdef MEMORY2_BASE
+register_phys_mem(MEMORY2_TYPE, MEMORY2_BASE, MEMORY2_SIZE);
+#endif
+#ifdef MEMORY3_BASE
+register_phys_mem_pgdir(MEMORY3_TYPE, MEMORY3_BASE, MEMORY3_SIZE);
+#endif
+#ifdef MEMORY4_BASE
+register_phys_mem(MEMORY4_TYPE, MEMORY4_BASE, MEMORY4_SIZE);
+#endif
+#ifdef MEMORY5_BASE
+register_phys_mem_pgdir(MEMORY5_TYPE, MEMORY5_BASE, MEMORY5_SIZE);
+#endif
+#ifdef MEMORY6_BASE
+register_phys_mem_pgdir(MEMORY6_TYPE, MEMORY6_BASE, MEMORY6_SIZE);
+#endif
+#ifdef MEMORY7_BASE
+register_phys_mem_pgdir(MEMORY7_TYPE, MEMORY7_BASE, MEMORY7_SIZE);
+#endif
+#ifdef MEMORY8_BASE
+register_phys_mem_pgdir(MEMORY8_TYPE, MEMORY8_BASE, MEMORY8_SIZE);
+#endif
+#ifdef DEVICE0_PA_BASE
+register_phys_mem_pgdir(DEVICE0_TYPE, DEVICE0_PA_BASE, DEVICE0_SIZE);
+#endif
+#ifdef DEVICE1_PA_BASE
+register_phys_mem_pgdir(DEVICE1_TYPE, DEVICE1_PA_BASE, DEVICE1_SIZE);
+#endif
+
+#ifdef CFG_SCIF
+static struct hscif_uart_data console_data __nex_bss;
+#endif
+
+#ifdef PRR_BASE
+uint32_t rcar_prr_value __nex_bss;
+#endif
+
+void plat_console_init(void)
+{
+	hscif_uart_init(&console_data, CONSOLE_UART_START);
+	register_serial_console(&console_data.chip);
+}
+
+#ifdef CFG_RCAR_ROMAPI
+/* Should only seed from a hardware random number generator */
+unsigned long plat_get_aslr_seed(void)
+{
+	unsigned long seed = 0;
+
+	/* On RCAR we can get hw random bytes on early boot stages */
+	if (crypto_rng_read(&seed, sizeof(seed)))
+		panic();
+
+	return seed;
+}
+#endif
+
+void boot_primary_init_intc(void)
+{
+	gic_init(GICC_BASE, GICD_BASE);
+}
+
+void boot_secondary_init_intc(void)
+{
+	gic_init_per_cpu();
+}
+
+#ifdef CFG_WITH_SOFTWARE_PRNG /* using the SW RNG supported*/
+void plat_rng_init(void)
+{
+	TEE_Result res = TEE_SUCCESS;
+	TEE_Time t = { };
+
+	res = crypto_rng_init(&t, sizeof(t));
+	if (res) {
+		EMSG("Failed to initialize RNG: %#" PRIx32, res);
+		panic();
+	}
+}
+#endif /*END CFG_WITH_SOFTWARE_PRNG */
+

core/arch/arm/plat-rcar_gen5/platform_config.h

@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2025, Renesas Electronics Corporation.
+ */
+
+#ifndef PLATFORM_CONFIG_H
+#define PLATFORM_CONFIG_H
+
+#define RCAR_CACHE_LINE_SZ		64
+#define CFG_RCAR_GEN5   1
+
+/* Make stacks aligned to data cache line length */
+#define STACK_ALIGNMENT		RCAR_CACHE_LINE_SZ
+
+#if defined(CFG_RCAR_GEN5)
+#define GICD_BASE              0x38000000
+
+#if CFG_RCAR_UART == 200	/* HSCIF0 */
+#define CONSOLE_UART_START	0xC0710000
+#endif
+/* config for MMU mapping */
+#define RCAR_SRAM_BASE		    0x8C300000U
+#define TZDRAM_BASE             RCAR_SRAM_BASE
+#define TZDRAM_SIZE             (0x02000000U) /* 1024*1024*32 */
+
+#define CFG_TEE_RAM_VA_SIZE         (1024 * 1024 * 3) /* = 300000*/
+#define TEE_RAM_START     (0x8C400000)  /* TEE RAM address */
+#define TEE_RAM_SIZE      (0x00300000U) /* TEE RAM size*/
+
+#ifdef CFG_TEE_RAM_VA_SIZE
+#ifdef CFG_WITH_PAGER
+#define TEE_RAM_PH_SIZE		TZSRAM_SIZE
+#else
+#define TEE_RAM_PH_SIZE		TEE_RAM_SIZE
+#endif
+#endif
+
+#ifndef TEE_LOAD_ADDR
+#define TEE_LOAD_ADDR   TEE_RAM_START
+#endif
+
+#define TA_RAM_START            (RCAR_SRAM_BASE	\
+				  + 0x400000U)   /* TA RAM address */
+#define TA_RAM_SIZE             (0x01400000U)	/* TA RAM size */
+
+#define TEE_SHMEM_START         (RCAR_SRAM_BASE	\
+				  + 0x3E00000U) /* Share Memory address */
+#define TEE_SHMEM_SIZE          (0x00100000U) /* Share Memory size    */
+
+#define OPTEE_LOG_BASE          (RCAR_SRAM_BASE	\
+				  + 0x1E00000U) /* OP-TEE Log Area address */
+#define OPTEE_LOG_NS_BASE       (RCAR_SRAM_BASE	\
+				  + 0x3F00000U) /* OP-TEE Log Area NS addr */
+#define OPTEE_LOG_NS_SIZE       (0x00014000U)   /* OP-TEE Log Area NS size */
+
+#define TA_VERIFICATION_BASE    (RCAR_SRAM_BASE	\
+				  + 0x1800000U) /* TA area for verification */
+#define TA_VERIFICATION_SIZE    (0x00100000U)   /* TA for verification size */
+
+#define NONCACHE_WORK_BASE      (RCAR_SRAM_BASE	\
+				 + 0x1F00000U) /* Non Cache Area address   */
+#define NONCACHE_WORK_SIZE      (0x00100000U)   /* Non Cache Area Size  */
+
+#define RSIPM_FW_SHMEM_BASE    (0x41C00000U) /* RSIPM FW Share Memory address */
+#define RSIPM_FW_SHMEM_SIZE    (0x00100000U) /* RSIPM FW Share Memory size */
+
+/* for Soc Register mapping function */
+#define MAP_DEVICE_REG_RCAR_BASE	(0xC0400000)
+#define MAP_DEVICE_REG_RCAR_SIZE	(0x1FC00000)
+
+#define LIFEC_BASE              (0x1C020000)    /* Life Cycle address   */
+#define PRR_BASE                (0xFFF00000U)   /* Product Register address */
+#define MFIS_BASE               (0x18800000U)   /* MFIS address */
+
+#define MEM_SECTION_SIZE        (0x00100000U)
+#ifdef CFG_WITH_LPAE
+#define MAX_XLAT_TABLES         CFG_MMAP_REGIONS
+#endif
+
+#define DEVICE0_PA_BASE	ROUNDDOWN(LIFEC_BASE, CORE_MMU_PGDIR_SIZE)
+#define DEVICE0_SIZE		(MEM_SECTION_SIZE)
+#define DEVICE0_TYPE		MEM_AREA_IO_SEC
+
+#define DEVICE1_PA_BASE		ROUNDDOWN(GICD_BASE, CORE_MMU_PGDIR_SIZE)
+#define DEVICE1_SIZE		(MEM_SECTION_SIZE * 9)
+#define DEVICE1_TYPE		MEM_AREA_IO_SEC
+
+/* LOG Area for Secure World */
+#define MEMORY1_BASE		ROUNDDOWN(OPTEE_LOG_BASE, MEM_SECTION_SIZE)
+#define MEMORY1_SIZE		(MEM_SECTION_SIZE)
+#define MEMORY1_TYPE		MEM_AREA_IO_SEC
+
+/* LOG Area for Normal World */
+#define MEMORY2_BASE           ROUNDDOWN(OPTEE_LOG_NS_BASE, MEM_SECTION_SIZE)
+#define MEMORY2_SIZE		(OPTEE_LOG_NS_SIZE)
+#define MEMORY2_TYPE		MEM_AREA_RAM_NSEC
+
+/* HSCIF address map area */
+#define MEMORY3_BASE           ROUNDDOWN(MAP_DEVICE_REG_RCAR_BASE, \
+					MAP_DEVICE_REG_RCAR_SIZE)
+#define MEMORY3_SIZE           (MAP_DEVICE_REG_RCAR_SIZE)
+#define MEMORY3_TYPE           MEM_AREA_IO_SEC
+
+/* TA area for verification */
+#define MEMORY4_BASE		ROUNDDOWN(TA_VERIFICATION_BASE, \
+					MEM_SECTION_SIZE)
+#define MEMORY4_SIZE		(TA_VERIFICATION_SIZE)
+#define MEMORY4_TYPE		MEM_AREA_IO_SEC
+
+/* Product Register (PRR) */
+#define MEMORY5_BASE		ROUNDDOWN(PRR_BASE, MEM_SECTION_SIZE)
+#define MEMORY5_SIZE		(MEM_SECTION_SIZE)
+#define MEMORY5_TYPE		MEM_AREA_IO_SEC
+
+/* Non Cache Stack Area */
+#define MEMORY6_BASE           ROUNDDOWN(NONCACHE_WORK_BASE, \
+					MEM_SECTION_SIZE)
+#define MEMORY6_SIZE		(MEM_SECTION_SIZE)
+#define MEMORY6_TYPE		MEM_AREA_IO_SEC
+
+/* ICU FW Share Memory Address Map */
+#define MEMORY7_BASE		ROUNDDOWN(RSIPM_FW_SHMEM_BASE, MEM_SECTION_SIZE)
+#define MEMORY7_SIZE		(RSIPM_FW_SHMEM_SIZE)
+#define MEMORY7_TYPE		MEM_AREA_IO_SEC
+
+/* MFIS Address Map */
+#define MEMORY8_BASE		ROUNDDOWN(MFIS_BASE, MEM_SECTION_SIZE)
+#define MEMORY8_SIZE		(MEM_SECTION_SIZE)
+#define MEMORY8_TYPE		MEM_AREA_IO_SEC
+#endif	/* CFG_RCAR_GEN5 */
+
+#endif /*PLATFORM_CONFIG_H*/

core/arch/arm/plat-rcar_gen5/rcar-common.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2025, Renesas Electronics Corporation
+ */
+
+#ifndef RCAR_COMMON_H
+#define RCAR_COMMON_H
+
+#include <string.h>
+#include <platform_config.h>
+#include <kernel/misc.h>
+#include <kernel/panic.h>
+#include <drivers/gic.h>
+#include <arm.h>
+#include <kernel/tee_time.h>
+#include <mm/core_memprot.h>
+
+/*
+ * Convert a physical address to a virtual address with the
+ * MEM_AREA_IO_SEC attribute.
+ */
+#define p2v_ioadr(r, len) ((vaddr_t)(phys_to_virt((r), MEM_AREA_IO_SEC, (len))))
+#define p2v_regadr(r, len) ((phys_to_virt((r), MEM_AREA_IO_SEC, (len))))
+
+/* RPC No specific to R-Car */
+#define TEE_RPC_DEBUG_LOG      (0x3F000000U)
+
+/* Product Register */
+#define PRR     p2v_ioadr(0xFFF00044U, MEMORY5_SIZE)
+
+/* Debug log output for test confirmation */
+#ifndef RCAR_TEST_LOG
+#define TMSG(...)   ((void)0)
+#else
+#define TMSG(...)   trace_printf_helper(TRACE_DEBUG, true, __VA_ARGS__)
+#endif /* RCAR_TEST_LOG */
+
+/*
+ * Define the information of debug log that communicates between Normal
+ * World and Secure World.
+ */
+#define SMC_RCAR_CMD           (12345U)
+
+#define START_DLOG_OUTPUT      (1U)
+
+/* Declaration of global variables */
+extern uint32_t product_type;
+extern const int8_t *product_name;
+extern uint32_t prr_cut;
+extern uint32_t cpu_on_core_lock;
+extern uint32_t cpu_on_core_bit;
+
+#endif /* RCAR_COMMON_H */

core/arch/arm/plat-rcar_gen5/rcar_version.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2025, Renesas Electronics Corporation.
+ */
+
+#ifndef RCAR_VERSION_H
+#define RCAR_VERSION_H
+
+#include <stdint.h>
+
+#define VERSION_OF_RENESAS	"1.0.0"
+
+#endif /* RCAR_VERSION_H */

core/arch/arm/plat-rcar_gen5/sub.mk

@@ -0,0 +1,2 @@
+global-incdirs-y += .
+srcs-y += main.c