Add support of CC1352P7

contrib/loaders/flash/cc26xx/flash.c

@@ -68,7 +68,7 @@ typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t);
 *
 ******************************************************************************/
 static void issue_fsm_command(flash_state_command_t command);
-static void enable_sectors_for_write(void);
+static void enable_sectors_for_write(uint32_t);
 static uint32_t scale_cycle_values(uint32_t specified_timing,
 	uint32_t scale_value);
 static void set_write_mode(void);
@@ -106,42 +106,51 @@ uint32_t flash_bank_erase(bool force_precondition)
 	uint32_t error_return;
 	uint32_t sector_address;
 	uint32_t reg_val;
+	uint32_t bank_no;
+	uint32_t top_bank_start_addr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) &
+					FLASH_FCFG_B1_START_B1_START_ADDR_M)
+					>> FLASH_FCFG_B1_START_B1_START_ADDR_S;
 
-	/* Enable all sectors for erase. */
-	enable_sectors_for_write();
+	for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
+		/* Enable all sectors for erase. */
+		enable_sectors_for_write(bank_no);
 
-	/* Clear the Status register. */
-	issue_fsm_command(FAPI_CLEAR_STATUS);
+		/* Clear the Status register. */
+		issue_fsm_command(FAPI_CLEAR_STATUS);
 
-	/* Enable erase of all sectors and enable precondition if required. */
-	reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
-	if (force_precondition)
-		HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
-			FLASH_FSM_ST_MACHINE_DO_PRECOND;
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		/* Enable erase of all sectors and enable precondition if required. */
+		reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE);
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000;
+		if (force_precondition)
+			HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |=
+				FLASH_FSM_ST_MACHINE_DO_PRECOND;
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
 
-	/* Issue the bank erase command to the FSM. */
-	issue_fsm_command(FAPI_ERASE_BANK);
+		// Write address to FADDR register.
+		HWREG(FLASH_BASE + FLASH_O_FADDR) = ADDR_OFFSET + (bank_no * top_bank_start_addr);
 
-	/* Wait for erase to finish. */
-	while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
-		;
+		/* Issue the bank erase command to the FSM. */
+		issue_fsm_command(FAPI_ERASE_BANK);
 
-	/* Update status. */
-	error_return = flash_check_fsm_for_error();
+		/* Wait for erase to finish. */
+		while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY)
+			;
 
-	/* Disable sectors for erase. */
-	flash_disable_sectors_for_write();
+		/* Update status. */
+		error_return = flash_check_fsm_for_error();
 
-	/* Set configured precondition mode since it may have been forced on. */
-	if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
-		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-		HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
-			~FLASH_FSM_ST_MACHINE_DO_PRECOND;
-		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		/* Set configured precondition mode since it may have been forced on. */
+		if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) {
+			HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+			HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &=
+				~FLASH_FSM_ST_MACHINE_DO_PRECOND;
+			HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		}
+
+		if (error_return != FAPI_STATUS_SUCCESS)
+			break;
 	}
 
 	/* Program security data to default values in the customer configuration */
@@ -154,6 +163,9 @@ uint32_t flash_bank_erase(bool force_precondition)
 							CCFG_SIZE_SECURITY);
 	}
 
+	/* Disable sectors for erase. */
+	flash_disable_sectors_for_write();
+
 	/* Return status of operation. */
 	return error_return;
 }
@@ -187,23 +199,34 @@ uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count)
 ******************************************************************************/
 void flash_disable_sectors_for_write(void)
 {
+	uint32_t bank_no;
+
 	/* Configure flash back to read mode */
 	set_read_mode();
 
-	/* Disable Level 1 Protection. */
-	HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
+	for (bank_no = 0; bank_no < flash_bank_count(); bank_no++) {
 
-	/* Disable all sectors for erase and programming. */
-	HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+		/* Select flash bank. */
+		HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
 
-	/* Enable Level 1 Protection. */
-	HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+		/* Disable Level 1 Protection. */
+		HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
 
-	/* Protect sectors from sector erase. */
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
-	HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
-	HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+		/* Disable all sectors for erase and programming. */
+		HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+
+		/* Enable Level 1 Protection. */
+		HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+
+		/* Protect sectors from sector erase. */
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
+		HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
+		HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+	}
+
+	// Select bank 0
+	HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x0;
 }
 
 /******************************************************************************
@@ -240,7 +263,7 @@ static void issue_fsm_command(flash_state_command_t command)
 * the FLASH_O_FSM_SECTOR1 register.
 *
 ******************************************************************************/
-static void enable_sectors_for_write(void)
+static void enable_sectors_for_write(uint32_t bank_no)
 {
 	/* Trim flash module for program/erase operation. */
 	trim_for_write();
@@ -249,7 +272,7 @@ static void enable_sectors_for_write(void)
 	set_write_mode();
 
 	/* Select flash bank. */
-	HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00;
+	HWREG(FLASH_BASE + FLASH_O_FMAC) = bank_no;
 
 	/* Disable Level 1 Protection. */
 	HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;

contrib/loaders/flash/cc26xx/flash.h

@@ -272,6 +272,46 @@ static inline uint32_t flash_check_fsm_for_ready(void)
 		return FAPI_STATUS_FSM_READY;
 }
 
+/******************************************************************************
+ *
+ * Get the number of banks
+ *
+ * This function returns the number of bank of the flash.
+ *
+ * Returns the number of banks
+ *
+ ******************************************************************************/
+static inline uint32_t flash_bank_count(void)
+{
+	uint32_t bank_count;
+
+	bank_count = (HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
+		FLASH_FCFG_BANK_MAIN_NUM_BANK_M) >>
+		FLASH_FCFG_BANK_MAIN_NUM_BANK_S;
+
+	return bank_count;
+}
+
+/******************************************************************************
+ *
+ * Get the size of the bank.
+ *
+ * This function returns the size of the main bank in number of bytes.
+ *
+ * Returns the flash size in number of bytes.
+ *
+ ******************************************************************************/
+static inline uint8_t flash_bank_width(void)
+{
+	uint8_t bank_width;
+
+	bank_width = (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) &
+		FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >>
+		FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3);
+
+	return bank_width;
+}
+
 /******************************************************************************
 *
 * Erase a flash sector.

contrib/loaders/flash/cc26xx/hw_regs.h

@@ -142,6 +142,10 @@
 /* FMC Sequential Pump Information */
 #define FLASH_O_FSEQPMP                                             0x000020A8
 
+#define FLASH_O_FADDR                                               0x00002110
+
+#define FLASH_O_FWPWRITE0                                           0x00002120
+
 /* FMC FSM Command */
 #define FLASH_O_FSM_CMD                                             0x0000220C
 
@@ -205,9 +209,14 @@
 /* FMC FSM Sector Erased  2 */
 #define FLASH_O_FSM_SECTOR2                                         0x000022C4
 
+#define FLASH_O_FCFG_BANK                                           0x00002400
+
 /* FMC Flash Bank 0 Starting Address */
 #define FLASH_O_FCFG_B0_START                                       0x00002410
 
+/* FMC Flash Bank 1 Starting Address */
+#define FLASH_O_FCFG_B1_START                                       0x00002414
+
 /* FMC Flash Bank 0 Sector Size 0 */
 #define FLASH_O_FCFG_B0_SSIZE0                                      0x00002430
 
@@ -1379,4 +1388,16 @@
 * 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */
 #define AON_PMCTL_PWRCTL_EXT_REG_MODE                               0x00000002
 
+/* Field:   [3:0] MAIN_NUM_BANK */
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0
+
+/* Field:  [23:0] B1_START_ADDR */
+#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0
+
+/* Field:  [15:4] MAIN_BANK_WIDTH */
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4
+
 #endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */

tcl/board/ti_cc26x2x7_launchpad.cfg

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# TI CC1352P7 LaunchPad Evaluation Kit
+#
+source [find interface/xds110.cfg]
+adapter speed 5500
+transport select jtag
+source [find target/ti_cc26x2x7.cfg]

tcl/target/ti_cc26x2x7.cfg

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Texas Instruments CC26x2 - ARM Cortex-M4
+#
+# http://www.ti.com
+#
+
+set CHIPNAME cc26x2x7
+set JRC_TAPID 0x1BB7702F
+set WORKAREASIZE 0x7000
+
+source [find target/ti_cc26x0.cfg]