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Add support for flashing efm32s2 targets.

Adding this based on the suggestion from zephyrproject-rtos/zephyr#88321 (comment) to get this into the Zephyr OpenOCD fork for easier flashing for these targets.

Add support for flashing efm32s2 targets.

Signed-off-by: Peter Johanson <[email protected]>
@silabs-bozont
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Having this support would also be great for flashing the Arduino Nano Matter natively.
Support for the Nano Matter is being added in: zephyrproject-rtos/zephyr#91661

@pillo79
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pillo79 commented Jan 13, 2026

@stephanosio gentle ping for review/merge of this PR - as @silabs-bozont mentioned, it's required to fully support flashing the Arduino Nano Matter board. There's now an outstanding Zephyr issue that will be closed with this.

@jerome-pouiller
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For information, I have tested this patch with seeed/xiao_mg24 and with silabs/xg24_rb4186c. I use this patch as a workaround for zephyrproject-rtos/sdk-ng#727.

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I have a bunch of Silabs boards. I plan to find a bit of time to test this PR in the next days.

{ 120, "EZR32WG Wonder", .series = 0 },
{ 121, "EZR32LG Leopard", .series = 0 },
{ 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
{ 128, "SERIES2V0", .series = 2 },

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Do you believe this river support Series-0 and Series-1? If yes, maybe it should replace the existing efm32 driver? (could be renamed in efm32_legacy?)

uint16_t page_size;
};

struct efm32x_flash_chip {

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About naming, the Silabs chips are named EFM32 or EFR32 (depending if they include a radio or not). I assume it's fine to name everything "efm32". However, what the 'x' stands for in 'efm32x'?

@stephanosio
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@stephanosio gentle ping for review/merge of this PR - as @silabs-bozont mentioned, it's required to fully support flashing the Arduino Nano Matter board. There's now an outstanding Zephyr issue that will be closed with this.

Please open a PR on sdk-ng pulling this patch.

@pillo79
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pillo79 commented Jan 15, 2026

Done: zephyrproject-rtos/sdk-ng#1059
Had to rebase this PR over current openocd, so I moved the PR to my fork. It's Martino's patch anyway 🙂

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I have tested this patch with success on xg21, xg23, xg24, x26, xg28 and xg29 (with fixes suggested in my comments).
It failed on xg22 and xg27 (with Error: timed out while waiting for target halted) and I have not been able to test on xg25.

set _FLASHBASE $FLASHBASE
} else {
set _FLASHBASE 0x00000000
}

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In fact, most of Series-2 start at 0x08000000. Only xg21 and xg22 start at 0x00000000 (source: grep FLASH_MEM_BASE in hal_silabs/simplicity_sdk/platform/Device). Probably you want to invert the logic.

# Silicon Labs (formerly Energy Micro) EFM32 target
#
# Note: All EFM32 chips have SWD support, but only newer series 1
# chips have JTAG support.

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This comment is probably out of date.

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Silabs references the various soc with xg21, xg22, xg23... (see zephyr/dts/arm/silabs). So I suggest to name this file silabs_xg23.cfg (or considering efm32.cfg already exist: efm32xg23.cfg).

# Family group 22 has flash base address 0x00000000
# Family group 23 has flash base address 0x08000000
set FLASHBASE 0x08000000
source [find target/efm32s2.cfg]

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This file is also compatible with xg24, xg26, xg28 and xg29. Do we want to create one file per family or find a common name for all of them?

efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
ret = efm32x_get_part_info(bank, efm32_info);
if (ret != ERROR_OK)
return ret;

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Trailing spaces

struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
struct efm32_info *efm32_mcu_info = &(efm32x_info->info);
int ret;
uint32_t base_address = EFM32_FLASH_BASE;

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FLASHBASE is already defined in the .cfg file. Is there any way to avoid duplication?

Otherwise, same comment applies: only xg21 and xg22 starts at 0x000000000.

msc_clken = EFM32_CMU_REG_CLKEN1_MSC_MSK_G23;
} else {
LOG_WARNING("Don't know EFR/EFM Gx family number, can't set MSC register. Defaulting to EF{M,R}xG22 values..");
}

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From the hal_silabs, we can found:

  • xg21 -> msc_clken == 0
  • xg22, xg27 and xg29 -> msc_clken == 17
  • xg23, xg25, xg25, xg26 and xg28 -> msc_clken == 16

I suggest to rename EFM32_CMU_REG_CLKEN1_MSC_MSK_* symbols and improve this condition.


proc efm32s2_dci_read_status {} {
set target [target current]
set dap [$target cget -dap]

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Indentation.


proc efm32s2_dci_connect {} {
set target [target current]
set dap [$target cget -dap]

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Indentation

return
}

poll off

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poll is disabled but never enabled again. This is the reason why it does not work on xg22. We have to call poll on after the calls to efm32s2_dci_write_cmd(), efm32s2_dci_read_response(), etc...

if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq

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It seems the problem with xg27 comes from the reset. It seems the line above does not work and we need a workaround. This is probably out of the scope of this PR.

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6 participants