cy8ckit_041s_max TCPWM_COUNTER Driver #101376
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Add support for PSOC 4100S Max series MCUs with 195 part numbers across 4 package variants (100-TQFP, 64-TQFP, 48-TQFP, 48-QFN). Signed-off-by: Braeden Lane <[email protected]>
Add devicetree support for PSOC 4100S Max series including: - Base SoC dtsi with GPIO, UART, HSIOM peripherals - Package-specific dtsi files for pin multiplexing - All 195 MPN-specific devicetree includes - Updated compatible strings for PSOC 4 support - Clock structure with clk_hf and clk_pump nodes - Simplified peripheral clock naming (peri_clk_div) - PSOC4xx clock source definitions and bindings Signed-off-by: Braeden Lane <[email protected]>
Add GPIO driver for Infineon PSOC 4 series MCUs using the Infineon PDL. Signed-off-by: Braeden Lane <[email protected]>
Add clock control and UART support for PSOC 4 family: - Clock control drivers with PSOC 4 compatibility - PSOC4xx clock source bindings and definitions - HF clock divider configuration support - UART FIFO trigger level configuration for PSOC 4100S Max series with 8-deep FIFO (RX trigger=7, TX trigger=0) Signed-off-by: Braeden Lane <[email protected]>
Add support for Infineon CY8CKIT-041S-MAX development kit based on CY8C4149AZI-S598 (PSoC 4100S Max). Board features: - 100-pin TQFP PSOC 4100S Max MCU (384KB Flash, 32KB SRAM) - User LED and button - KitProg3 for programming/debugging - Common dtsi structure for peripheral configuration Signed-off-by: Braeden Lane <[email protected]>
Add test and sample overlays for CY8CKIT-041S-MAX board: - GPIO basic API test using P1.2 and P1.3 pins - Button sample using P11.5 with pull-up configuration Signed-off-by: Braeden Lane <[email protected]>
Add implementation of the Infineon PSoC4 TCPWM-based counter driver. - Provides basic counter operations including start, stop, read, and set alarm. - Supports configuration and initialization through Device Tree. - Enables alarm callback handling for precise time-based event generation. Signed-off-by: Braeden Lane <[email protected]>
Add device tree overlay configuration for the Infineon PSoC4100S Max board to enable the counter alarm sample. The overlay configures TCPWM0_1 for counter operation with interrupt 18 and clock divider settings appropriate for the PSoC4100S Max chip. Signed-off-by: Braeden Lane <[email protected]>
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This PR will be marked DRAFT until the following PRs are merged:
Also relates to #100952