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Fix replication operator syntax in Verilog module#6

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Shivaaaydv wants to merge 1 commit intoAdrofier:mainfrom
Shivaaaydv:patch-1
Open

Fix replication operator syntax in Verilog module#6
Shivaaaydv wants to merge 1 commit intoAdrofier:mainfrom
Shivaaaydv:patch-1

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Commits on Dec 3, 2025