linux: How_to_Guides: Add instructions to enable SSC on DSS PLLs #529
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bluehyperX
requested review from
StaticRocket,
VeeruPrudhvi,
aniket-l,
cshilwant,
praneethbajjuri and
uditkumarti
as code owners
Add comprehensive how-to guide for enabling Spread Spectrum Clocking (SSC) on Display Subsystem (DSS) Phase-locked loops (PLLs). The guide covers: - SSC configuration parameters via device tree - Three configuration examples (center spread, down spread, greater depth) - Supported SoCs: AM62x, AM62Ax, AM62Dx, AM62Px - Troubleshooting and best practices - Customer responsibilities Signed-off-by: Sparsh Kumar <[email protected]>
| Documentation for tidss device tree node and its properties can be found in linux kernel device tree bindings in below directory | ||
| ``Documentation/devicetree/bindings/display/ti/``. Seperate binding files are present for different version of the DSS controller. | ||
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| For information about configuring Spread Spectrum Clocking (SSC) for DSS, see <../../../../How_to_Guides/Target/How_to_enable_SSC_for_DSS.html>`__ |
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use :ref: for cross referencing [0]
eg - checkout [1]
[0] - https://www.sphinx-doc.org/en/master/usage/referencing.html#role-ref
| This guide shows how to configure SSC for DSS pixel clocks on supported TI SoCs. | ||
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| .. important:: | ||
| The pixel clock frequency for DPI from the DSS PLL must not exceed 165MHz. Center spread adds a 20% overshoot to the modulation depth. Account for this when you calculate the maximum frequency. |
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Make sure that the directive and the content block have 1 new line between them and that the content block has at least 1 newline after it.
| The modulation uses a triangular waveform. The Device Manager automatically configures the PLL hardware based on the modulation frequency specified in the device tree. | ||
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| .. note:: | ||
| Down spread mode (value 3) is commonly used for display interfaces. It ensures the clock never exceeds the specified maximum frequency. This is important for meeting display timing specifications and avoiding over-clocking. |
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| Down spread mode (value 3) is commonly used for display interfaces. It ensures the clock never exceeds the specified maximum frequency. This is important for meeting display timing specifications and avoiding over-clocking. | ||
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| .. note:: | ||
| SSC is currently supported only on display PLL for these SoCs: AM62x, AM62Ax, AM62Dx, AM62Px. The display PLL is typically PLL17. You can also use PLL16 or PLL18 for DPI applications. |
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| SSC is currently supported only on display PLL for these SoCs: AM62x, AM62Ax, AM62Dx, AM62Px. The display PLL is typically PLL17. You can also use PLL16 or PLL18 for DPI applications. | ||
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| .. note:: | ||
| The Device Manager automatically converts the modulation depth values from the device tree to the appropriate hardware register values. |
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| }; | ||
| .. note:: | ||
| Greater modulation depth provides better EMI reduction but increases clock jitter. Test with your specific display panel to ensure timing margins meet requirements. |
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| References | ||
| ---------- | ||
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| - `DSS Driver Documentation <../../Foundational_Components/Kernel/Kernel_Drivers/Display/DSS7.html>`__ |
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use :ref: for cross referencing [0]
eg - checkout [1]
[0] - https://www.sphinx-doc.org/en/master/usage/referencing.html#role-ref
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| .. _how-to-enable-ssc-for-dss: | |||
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| How to enable spread spectrum clocking for display subsystem | |||
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This entire new file doesn't seem to follow sphinx guidelines for section headers
for instance, How to enable spread spectrum clocking for display subsystem should be treated as parts.
Likewise, please plan to update the below section headers accordingly.
https://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html#sections
| - Modulation depth: 10 (0.1%) | ||
| - Spread type: Center spread (1) | ||
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| Add the following properties to the DSS node in your device tree file (for example, ``k3-am62p-j722s-common-main.dtsi``): |
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| Add the following properties to the DSS node in your device tree file (for example, ``k3-am62p-j722s-common-main.dtsi``): | |
| Add the following properties to the DSS node in your device tree file (for example, :file:`k3-am62p-j722s-common-main.dtsi`): |
https://www.sphinx-doc.org/en/master/usage/restructuredtext/roles.html#role-file
| 4. Work with the display panel vendor to resolve any issues caused by enabling SSC | ||
| 5. Validate displays to have enough functional margin with the jitter introduced by spread spectrum modulation | ||
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| Some display panels have clocking limitations not in their data sheets. Work directly with the display panel manufacturer on any display-related issues from SSC. |
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did you mean?
| Some display panels have clocking limitations not in their data sheets. Work directly with the display panel manufacturer on any display-related issues from SSC. | |
| Some display panels have clocking limitations not mentioned in their data sheets. Work directly with the display panel manufacturer on any display-related issues from SSC. |
| linux/How_to_Guides/Target/How_to_enable_DT_overlays_in_linux | ||
| linux/How_to_Guides/Target/How_To_Enable_M2CC3301_in_linux | ||
| linux/How_to_Guides/Target/How_to_playback_audio_over_HDMI | ||
| linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS |
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Do we need a similar guide for AM62L as well?
| Introduction | ||
| ------------ | ||
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| Spread Spectrum Clocking (SSC) reduces electromagnetic interference (EMI). It modulates the clock frequency. SSC varies the frequency over time. This spreads energy across many frequencies. This reduces peak emissions. |
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Spread Spectrum Clocking (SSC) is an EMI reduction technique that:
Modulates the clock frequency rather than keeping it constant
Varies the frequency over time in a controlled manner
Spreads energy across multiple frequencies instead of concentrating it at a single frequency
Reduces peak emissions by distributing the electromagnetic energy
This is a common technique used in electronic systems, particularly in high-speed digital circuits, to help meet EMI compliance requirements without requiring additional shielding or filtering components.
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| Spread Spectrum Clocking (SSC) reduces electromagnetic interference (EMI). It modulates the clock frequency. SSC varies the frequency over time. This spreads energy across many frequencies. This reduces peak emissions. | ||
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| Digital clock signals are periodic and square-shaped. Most energy focuses at the center frequency and odd harmonics. SSC spreads this energy across a wider range. This reduces the peak amplitude. SSC adds jitter to the clock signal. The voltage amplitude stays unchanged. |
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These look like single points and not paragraph.
Most of the energy is focused at the center frequency and odd harmonics, SSC redistributes this energy across a wider range by adding a jitter to clock signal thus reducing the peak amplitude.
The voltage amplitude stays unchanged -> Do you mean to say that average amplitude stays the same?
| .. code-block:: dts | ||
| &dss0 { | ||
| assigned-clocks = <&k3_clks 186 2>; |
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The SSC is only for output DPI clock and not for functional clock ?
| - ``assigned-clock-sscs``: Configures SSC with 100 kHz modulation, 0.1% depth, center spread mode (1) | ||
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| .. warning:: | ||
| This example uses center spread mode (1). Center spread has a 20% overshoot on the modulation depth. For 0.1% nominal depth, the actual peak deviation is about 0.12%. |
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Center spread has a 20% overshoot on the modulation depth. -> Is this documented somewhere?
For 0.1% nominal depth, the actual peak deviation is about 0.12% -> Is this documented somewhere?
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| When using center spread: | ||
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| 1. Ensure the display panel can handle the higher peak frequency |
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How to estimate highest peak frequency as per current modulation params?
| Display artifacts | ||
| ^^^^^^^^^^^^^^^^^ | ||
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| If you observe display artifacts, flickering, or other visual anomalies after enabling SSC: |
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Do we have some data on any observed side effects after going above X modulation ?
Also did we do some internal testing with refresh rate logs enabled to see if any jitter in refresh rate with suggested/example params showed in this doc ?
You can test that with kmstest --flip.
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| **You assume all responsibility for the configuration and usage of spread-spectrum clocking.** You must: | ||
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| 1. Research the clock limitations associated with your selected display panel |
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what about HDMI monitors?
6 participants
Add information on spread spectrum clocking (SSC) and how to enable it for DSS PLLs as a How_to_Guide.