Merge of function black boxing #4588
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…n. Still need to work on propagation to smtlib model.
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Indeed there a lot of left-over debug prints, but let's focus on the fundamental approach first. I have only skimmed the changes, but is the basic idea that function calls are deferred, that is they are converted to $fun cells in the frontend, and the user has the option to either blackbox those or replace them with the function's body later on?
| @@ -263,7 +265,7 @@ namespace AST | |||
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| // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc. | |||
| // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL() | |||
| bool simplify(bool const_fold, int stage, int width_hint, bool sign_hint); | |||
| bool simplify(bool const_fold, int stage, int width_hint, bool sign_hint, bool in_param, bool aux_modules = false); | |||
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This seems to partially revert #3813 and is introducing a new flag, which we want to avoid if it can be helped
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| RTLIL::Module *module; | ||
| RTLIL::IdString name; | ||
| AST::AstNode *def; |
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As far as I can tell this new Function object is here so that the ASTs of functions can be looked up. What is the AST used for?
This is adding a new type of member to modules (next to wires, cells, processes and memories). This means these now have to be considered all over the Yosys codebase anywhere we are manipulating modules and they should be saved/restored on writing out an RTLIL file.
That's a substantial addition in complexity to serve one feature. Preferably we encode what we need in parameters of the new cell type $fun instead (if we need a new cell type in the first place).
What are the reasons/motivation for this change?
I added a new feature to allow Verilog functions to be black boxed. In the generated smt2 file, an euf symbol is used instead
of expanding the function definition. Check out my Linkedin blog here https://www.linkedin.com/feed/update/urn:li:activity:7191433053066448896/. This blog links to earlier blogs describing the changes.
Explain how this is achieved.
Many changes to code generation.
If applicable, please suggest to reviewers how they can test the change.
I expect to do a lot of cleanup before these changes are accepted.
There are lots of debugging prints that should be removed. It would be good for someone with lots of experience with the internals of Yosys to review.