dump: add --sorted flag

[widlarizer]

This is helpful for diffs when roundtripping. The sort is somewhat imperfect as sorting the connections uses SigSpec operator< which doesn't result in a nice ordering. However, this comes into play only if the connections aren't equivalent, like here:

Therefore for getting a nice diff to check total complete equivalence excluding ordering even though opt_clean reordered your design (#3426) this is is still useful

• add test

[widlarizer]

Simplified repro for the above example:

module alu(
	input [7:0] A,
	input [7:0] B,
	output [7:0] result,
);
	assign result = A + B;
	wire [1:0] p1, p2;
	assign p1 = 2'bx1;
	assign p2[0] = 1'b1;
endmodule

read_verilog add.v
proc
dump --sorted -o before.il
bufnorm -nomode -buf
simplemap t:$buf t:$concat %u t:$slice %u
dump --sorted -o after.il