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Add --no-private-id-locs and new NEW_ID macro #5352

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6b9082f
driver: add --no-private-id-locs and NEWER_ID
widlarizer Sep 16, 2025
73d51b2
s/NEW_ID/NEWER_ID/g
widlarizer Sep 16, 2025
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8 changes: 4 additions & 4 deletions backends/aiger2/aiger.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1040,7 +1040,7 @@ struct XAigerWriter : AigerWriter {
for (auto [cursor, box, def] : opaque_boxes)
append_box_ports(box, cursor, false);

holes_module = design->addModule(NEW_ID);
holes_module = design->addModule(NEWER_ID);
std::vector<RTLIL::Wire *> holes_pis;
int boxes_ci_num = 0, boxes_co_num = 0;

Expand All @@ -1058,7 +1058,7 @@ struct XAigerWriter : AigerWriter {

for (auto [cursor, box, def] : nonopaque_boxes) {
// use `def->name` not `box->type` as we want the derived type
Cell *holes_wb = holes_module->addCell(NEW_ID, def->name);
Cell *holes_wb = holes_module->addCell(NEWER_ID, def->name);
int holes_pi_idx = 0;

if (map_file.is_open()) {
Expand Down Expand Up @@ -1097,7 +1097,7 @@ struct XAigerWriter : AigerWriter {
SigSpec in_conn;
for (int i = 0; i < port->width; i++) {
while (holes_pi_idx >= (int) holes_pis.size()) {
Wire *w = holes_module->addWire(NEW_ID, 1);
Wire *w = holes_module->addWire(NEWER_ID, 1);
w->port_input = true;
holes_module->ports.push_back(w->name);
holes_pis.push_back(w);
Expand Down Expand Up @@ -1126,7 +1126,7 @@ struct XAigerWriter : AigerWriter {
boxes_ci_num += port->width;

// holes
Wire *w = holes_module->addWire(NEW_ID, port->width);
Wire *w = holes_module->addWire(NEWER_ID, port->width);
w->port_output = true;
holes_module->ports.push_back(w->name);
holes_wb->setPort(port_id, w);
Expand Down
2 changes: 1 addition & 1 deletion backends/verilog/verilog_backend.cc
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Expand Up @@ -2372,7 +2372,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
}
f << stringf(");\n");
if (!systemverilog && !module->processes.empty()) {
initial_id = NEW_ID;
initial_id = NEWER_ID;
f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
}

Expand Down
6 changes: 3 additions & 3 deletions docs/source/code_examples/extensions/my_cmd.cc
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Expand Up @@ -38,9 +38,9 @@ struct Test1Pass : public Pass {
y->port_output = true;
y->port_id = 2;

RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
module->addNeg(NEW_ID, a, a_inv, true);
module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
RTLIL::Wire *a_inv = module->addWire(NEWER_ID, 4);
module->addNeg(NEWER_ID, a, a_inv, true);
module->addMux(NEWER_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);

module->fixup_ports();
}
Expand Down
10 changes: 5 additions & 5 deletions frontends/aiger/aigerparse.cc
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Expand Up @@ -559,9 +559,9 @@ void AigerReader::parse_aiger_ascii()
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);

if (clk_wire)
module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
module->addDffGate(NEWER_ID, clk_wire, d_wire, q_wire);
else
module->addFfGate(NEW_ID, d_wire, q_wire);
module->addFfGate(NEWER_ID, d_wire, q_wire);

// Reset logic is optional in AIGER 1.9
if (f.peek() == ' ') {
Expand Down Expand Up @@ -683,9 +683,9 @@ void AigerReader::parse_aiger_binary()
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);

if (clk_wire)
module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
module->addDff(NEWER_ID, clk_wire, d_wire, q_wire);
else
module->addFf(NEW_ID, d_wire, q_wire);
module->addFf(NEWER_ID, d_wire, q_wire);

// Reset logic is optional in AIGER 1.9
if (f.peek() == ' ') {
Expand Down Expand Up @@ -795,7 +795,7 @@ void AigerReader::post_process()
log_assert(q->port_input);
q->port_input = false;

Cell* ff = module->addFfGate(NEW_ID, d, q);
Cell* ff = module->addFfGate(NEWER_ID, d, q);
ff->attributes[ID::abc9_mergeability] = mergeability[i];
q->attributes[ID::init] = initial_state[i];
}
Expand Down
10 changes: 5 additions & 5 deletions frontends/ast/genrtlil.cc
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Expand Up @@ -822,7 +822,7 @@ struct AST_INTERNAL::ProcessGenerator

RTLIL::SigSpec check = ast->children[0]->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap());
if (GetSize(check) != 1)
check = current_module->ReduceBool(NEW_ID, check);
check = current_module->ReduceBool(NEWER_ID, check);

Wire *en = current_module->addWire(cellname.str() + "_EN", 1);
set_src_attr(en, ast);
Expand Down Expand Up @@ -1626,11 +1626,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(fake_ast_width, fake_ast_sign);

if (source_offset != 0) {
shift_val = current_module->Sub(NEW_ID, shift_val, source_offset, fake_ast_sign);
shift_val = current_module->Sub(NEWER_ID, shift_val, source_offset, fake_ast_sign);
fake_ast->children[1]->is_signed = true;
}
if (id2ast->range_swapped) {
shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign);
shift_val = current_module->Sub(NEWER_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign);
fake_ast->children[1]->is_signed = true;
}
if (GetSize(shift_val) >= 32)
Expand Down Expand Up @@ -2028,7 +2028,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)

RTLIL::SigSpec check = children[0]->genRTLIL();
if (GetSize(check) != 1)
check = current_module->ReduceBool(NEW_ID, check);
check = current_module->ReduceBool(NEWER_ID, check);

RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
set_src_attr(cell, this);
Expand Down Expand Up @@ -2130,7 +2130,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} else if (arg->is_signed) {
// non-trivial signed nodes are indirected through
// signed wires to enable sign extension
RTLIL::IdString wire_name = NEW_ID;
RTLIL::IdString wire_name = NEWER_ID;
RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig));
wire->is_signed = true;
current_module->connect(wire, sig);
Expand Down
24 changes: 12 additions & 12 deletions frontends/blif/blifparse.cc
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Expand Up @@ -363,19 +363,19 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto no_latch_clock;

if (!strcmp(edge, "re"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
cell = module->addDff(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "fe"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
cell = module->addDff(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else if (!strcmp(edge, "ah"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
cell = module->addDlatch(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "al"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
cell = module->addDlatch(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else {
no_latch_clock:
if (dff_name.empty()) {
cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
cell = module->addFf(NEWER_ID, blif_wire(d), blif_wire(q));
} else {
cell = module->addCell(NEW_ID, dff_name);
cell = module->addCell(NEWER_ID, dff_name);
cell->setPort(ID::D, blif_wire(d));
cell->setPort(ID::Q, blif_wire(q));
}
Expand All @@ -394,7 +394,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto error;

IdString celltype = RTLIL::escape_id(p);
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
RTLIL::Cell *cell = module->addCell(NEWER_ID, celltype);
RTLIL::Module *cell_mod = design->module(celltype);

dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
Expand Down Expand Up @@ -441,7 +441,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (it.second.count(idx))
sig.append(it.second.at(idx));
else
sig.append(module->addWire(NEW_ID));
sig.append(module->addWire(NEWER_ID));
}

cell->setPort(it.first, sig);
Expand Down Expand Up @@ -517,7 +517,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool

if (sop_mode)
{
sopcell = module->addCell(NEW_ID, ID($sop));
sopcell = module->addCell(NEWER_ID, ID($sop));
sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
sopcell->parameters[ID::DEPTH] = 0;
sopcell->parameters[ID::TABLE] = RTLIL::Const();
Expand All @@ -533,7 +533,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
}
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($lut));
cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->setPort(ID::A, input_sig);
Expand Down Expand Up @@ -586,8 +586,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
sopmode = (*output == '1');
if (!sopmode) {
SigSpec outnet = sopcell->getPort(ID::Y);
SigSpec tempnet = module->addWire(NEW_ID);
module->addNotGate(NEW_ID, tempnet, outnet);
SigSpec tempnet = module->addWire(NEWER_ID);
module->addNotGate(NEWER_ID, tempnet, outnet);
sopcell->setPort(ID::Y, tempnet);
}
} else
Expand Down
2 changes: 1 addition & 1 deletion frontends/json/jsonparse.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -549,7 +549,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
if (bitval_node->type == 'N') {
int bitidx = bitval_node->data_number;
if (signal_bits.count(bitidx) == 0)
signal_bits[bitidx] = module->addWire(NEW_ID);
signal_bits[bitidx] = module->addWire(NEWER_ID);
sig.append(signal_bits.at(bitidx));
} else
log_error("JSON cells node '%s' connection '%s' has invalid bit value on bit %d.\n",
Expand Down
52 changes: 26 additions & 26 deletions frontends/liberty/liberty.cc
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Expand Up @@ -58,15 +58,15 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
int top = int(stack.size())-1;

if (0 <= top-1 && stack[top].type == 0 && stack[top-1].type == '!') {
token_t t = token_t(0, module->NotGate(NEW_ID, stack[top].sig));
token_t t = token_t(0, module->NotGate(NEWER_ID, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.push_back(t);
return true;
}

if (0 <= top-1 && stack[top].type == '\'' && stack[top-1].type == 0) {
token_t t = token_t(0, module->NotGate(NEW_ID, stack[top-1].sig));
token_t t = token_t(0, module->NotGate(NEWER_ID, stack[top-1].sig));
stack.pop_back();
stack.pop_back();
stack.push_back(t);
Expand All @@ -81,7 +81,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
}

if (0 <= top-2 && stack[top-2].type == 1 && stack[top-1].type == '^' && stack[top].type == 1) {
token_t t = token_t(1, module->XorGate(NEW_ID, stack[top-2].sig, stack[top].sig));
token_t t = token_t(1, module->XorGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.pop_back();
Expand All @@ -97,15 +97,15 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
}

if (0 <= top-1 && stack[top-1].type == 2 && stack[top].type == 2) {
token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-1].sig, stack[top].sig));
token_t t = token_t(2, module->AndGate(NEWER_ID, stack[top-1].sig, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.push_back(t);
return true;
}

if (0 <= top-2 && stack[top-2].type == 2 && (stack[top-1].type == '*' || stack[top-1].type == '&') && stack[top].type == 2) {
token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-2].sig, stack[top].sig));
token_t t = token_t(2, module->AndGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.pop_back();
Expand All @@ -121,7 +121,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
}

if (0 <= top-2 && stack[top-2].type == 3 && (stack[top-1].type == '+' || stack[top-1].type == '|') && stack[top].type == 3) {
token_t t = token_t(3, module->OrGate(NEW_ID, stack[top-2].sig, stack[top].sig));
token_t t = token_t(3, module->OrGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
stack.pop_back();
stack.pop_back();
stack.pop_back();
Expand Down Expand Up @@ -183,11 +183,11 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
{
RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);

RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($tribuf));
cell->setParam(ID::WIDTH, GetSize(func));
cell->setPort(ID::A, func);
cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state));
cell->setPort(ID::Y, module->addWire(NEW_ID));
cell->setPort(ID::EN, module->NotGate(NEWER_ID, three_state));
cell->setPort(ID::Y, module->addWire(NEWER_ID));
return cell->getPort(ID::Y);
}

Expand Down Expand Up @@ -236,11 +236,11 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
}
}

RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);

cell = module->addCell(NEW_ID, "");
cell = module->addCell(NEWER_ID, "");
cell->setPort(ID::D, data_sig);
cell->setPort(ID::Q, iq_sig);
cell->setPort(ID::C, clk_sig);
Expand Down Expand Up @@ -319,7 +319,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
}
}

RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);

Expand All @@ -330,25 +330,25 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla

if (clear_polarity == true || clear_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *inv = module->addCell(NEWER_ID, ID($_NOT_));
inv->setPort(ID::A, clear_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
inv->setPort(ID::Y, module->addWire(NEWER_ID));

if (clear_polarity == true)
clear_negative = inv->getPort(ID::Y);
if (clear_polarity != enable_polarity)
clear_enable = inv->getPort(ID::Y);
}

RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
RTLIL::Cell *data_gate = module->addCell(NEWER_ID, ID($_AND_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, clear_negative);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
data_gate->setPort(ID::Y, data_sig = module->addWire(NEWER_ID));

RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
RTLIL::Cell *enable_gate = module->addCell(NEWER_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, clear_enable);
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEWER_ID));
}

if (preset_sig.size() == 1)
Expand All @@ -358,28 +358,28 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla

if (preset_polarity == false || preset_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *inv = module->addCell(NEWER_ID, ID($_NOT_));
inv->setPort(ID::A, preset_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
inv->setPort(ID::Y, module->addWire(NEWER_ID));

if (preset_polarity == false)
preset_positive = inv->getPort(ID::Y);
if (preset_polarity != enable_polarity)
preset_enable = inv->getPort(ID::Y);
}

RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
RTLIL::Cell *data_gate = module->addCell(NEWER_ID, ID($_OR_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, preset_positive);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
data_gate->setPort(ID::Y, data_sig = module->addWire(NEWER_ID));

RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
RTLIL::Cell *enable_gate = module->addCell(NEWER_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, preset_enable);
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEWER_ID));
}

cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell = module->addCell(NEWER_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->setPort(ID::D, data_sig);
cell->setPort(ID::Q, iq_sig);
cell->setPort(ID::E, enable_sig);
Expand Down Expand Up @@ -734,7 +734,7 @@ struct LibertyFrontend : public Frontend {
if (wi->port_input) {
for (auto wo : module->wires())
if (wo->port_output) {
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
RTLIL::Cell *spec = module->addCell(NEWER_ID, ID($specify2));
spec->setParam(ID::SRC_WIDTH, wi->width);
spec->setParam(ID::DST_WIDTH, wo->width);
spec->setParam(ID::T_FALL_MAX, 1000);
Expand Down
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